Dual Capacitor Array SAR ADC for Lower Power and Chip Area
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Solution Overview
Problem
High-resolution analog-to-digital converters (ADCs) for neural interface systems face challenges in reducing power consumption and chip area due to the exponential increase in total capacitance and area requirements as the number of bits increases, with existing power reduction techniques only offering limited improvements.
Innovation Solution
The implementation of a dual capacitor array SAR ADC, where two smaller capacitor arrays are used instead of a single larger one, allowing for successive approximation iterations on both sides of the comparator inputs, reducing total capacitance and area by a factor of 2(n/2)−1, and incorporating a buffer stage to suppress kickback effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a single large capacitor array is used to achieve high resolution, then conversion precision is improved, but chip area and power consumption increase exponentially
Solution Approach 1:
The patent divides the single large capacitor array into two separate capacitor arrays (first and second capacitor arrays). Each array handles a portion of the binary-weighted capacitors, allowing the total capacitance to be distributed across separate physical structures. This segmentation reduces the area requirement for each individual array while maintaining the overall high-resolution conversion capability through coordinated operation of both arrays.
2Measurement precision
If a single large capacitor array is used to achieve high resolution, then conversion precision is improved, but power consumption increases
Solution Approach 1:
By segmenting the capacitor array into two smaller arrays, the patent reduces the total power consumption. Each smaller array requires less charge/discharge current during the successive approximation process, and the distributed architecture allows for more efficient power management. The dual-array structure enables parallel operation that reduces the overall energy required for high-resolution conversion.
3Measurement precision
If more bits are added to increase resolution, then measurement precision is improved, but total capacitance and area requirements increase exponentially
Solution Approach 1:
The patent implements a dual capacitor array architecture where the total capacitance is divided between two arrays. For an n-bit ADC, each array handles approximately n/2 bits of the binary-weighted capacitors. This segmentation allows the system to achieve high resolution without requiring a single large capacitor array with exponentially increasing total capacitance, as the capacitance is distributed and managed in two separate structures.
Solution Approach 2:
The patent transitions from a single-dimensional capacitor array structure to a two-dimensional dual-array configuration. By adding the dimension of a second capacitor array, the system can achieve the same or better resolution with reduced total capacitance requirements, as the capacitance is distributed across two independent structures rather than concentrated in one array.
Data Source
AI summary
An analog to digital converter that comprises a successive approximation register (SAR) having an n bit binary output, a first capacitor array connected to receive some of the bits of the binary output, a second capacitor array connected to receive the remaining bits of the binary output, and a comparator including an output connected to the SAR. The first and second capacitor arrays each have an analog output indicative of the charge stored by capacitors of that array. The comparator includes a pair of inputs, one of which is connected to the analog output of the first capacitor array and the other of which is connected to the analog output of the second capacitor array.