Floating-Gate Memory Cells with Dual Assistance Elements for Fast Write-Erase
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in achieving efficient rewriting operations, including erasing and writing at lower voltages in shorter times, while also requiring reduced memory cell areas.
Innovation Solution
The semiconductor device incorporates a memory cell with a memory element and two assistance elements, each comprising impurity regions and gates, which are electrically connected to the floating gate, allowing for efficient erasing and writing operations by increasing the potential of the floating gate using the assistance elements, thereby enhancing current flow and hot carrier generation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional memory cell structures are used, then the device complexity is low, but the operation efficiency (writing and erasing speed) is insufficient
Solution Approach 1:
The memory cell is segmented into multiple functional components: memory element (with selection gate and floating gate), first assistance element (with first gate connected to floating gate), and second assistance element (with second gate connected to floating gate). This segmentation allows independent control of writing and erasing operations through different assistance elements, improving operation efficiency without requiring complete redesign of the entire memory structure.
Solution Approach 2:
The first and second assistance elements act as intermediary structures that facilitate efficient charge transfer to the floating gate. The first assistance element (first impurity region and first gate) serves as an intermediary for writing operations, while the second assistance element (second impurity region and second gate) serves as an intermediary for erasing operations, enabling faster charge injection and extraction.
2Speed
If higher voltages are used for writing and erasing operations, then the operation speed increases, but the energy consumption and device stress increase
Solution Approach 1:
The patent employs parameter changes by applying different voltage levels to different gates during writing and erasing operations. During writing, the selection gate receives a first voltage and the first gate receives a second voltage to enable efficient charge injection. During erasing, the selection gate receives a third voltage and the second gate receives a fourth voltage. This parameter variation allows optimized operation speeds without requiring uniformly high voltages across all components, thereby reducing overall energy consumption and device stress.
3Area of stationary object
If memory cell area is reduced, then the device density increases, but the operation efficiency may be compromised
Solution Approach 1:
The first and second assistance elements are merged into the memory cell structure, with their gates (first gate and second gate) electrically connected to the floating gate. This merging allows the assistance elements to share the floating gate resource, enabling efficient writing and erasing operations within a compact area. The impurity regions are strategically positioned to provide assistance functions without significantly increasing the overall memory cell footprint.
Solution Approach 2:
The assistance elements are positioned in spatial dimensions that optimize their function while minimizing area increase. The first impurity region and second impurity region are placed in specific locations relative to the memory element, allowing them to provide electrical assistance through field effects rather than requiring direct physical contact or large overlapping areas, thus maintaining compact cell dimensions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables efficient writing and erasing operations in shorter times with reduced memory cell areas, minimizing charge trapping in the gate insulating film and improving data retention characteristics.
Implementation Method 1
The second gate is electrically connected to the floating gate
Implementation Method 2
enhancing current flow and hot carrier generation
Data Source
AI summary
A semiconductor device includes a memory cell on a semiconductor substrate. The memory cell includes a memory element, a first assistance element, and a second assistance element. The memory element includes a source region and a drain region, and a selection gate and a floating gate in series therebetween. The first assistance element includes a first impurity region and a first gate. The second assistance element includes a second impurity region and a second gate. The first and second gates are electrically connected to the floating gate. The second impurity region is connected to a signal line that is connected to the drain region or a signal line that is connected to the selection gate.