Dual-Banked Translation Buffering Circuitry for Address Translation
Solution Overview
Problem
Current memory address translation systems in data processing systems are inefficient in terms of power consumption and circuit area, and they face challenges in achieving fast translation times while maintaining performance.
Innovation Solution
The system employs a dual-banked translation buffering circuitry with a primary and secondary storage bank accessed in parallel, where the buffering management circuitry transfers entries based on occupancy levels, allowing for flexible management of translation entries and reducing the amount of information stored in each entry to save area and power.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a translation lookaside buffer is used to store virtual to physical address translations, then address translation speed is improved, but circuit area and power consumption increase
Solution Approach 1:
The translation buffering circuitry is divided into two separate storage banks: a first storage bank and a second storage bank. Each bank stores a subset of translation entries, allowing parallel access to reduce translation time while distributing the total storage capacity across two smaller units, thereby reducing the area overhead of a single large buffer.
2Productivity
If more translation entries are stored in the translation lookaside buffer, then translation hit rate is improved, but power consumption and circuit area increase
Solution Approach 1:
Translation entries are distributed across two storage banks, allowing the system to maintain a high hit rate by having multiple entries available in parallel while avoiding the power overhead of a single large buffer. The segmented structure enables selective activation and management of storage resources.
Solution Approach 2:
The system dynamically manages translation entries between the two storage banks based on occupancy levels. When one bank becomes full, entries are transferred to the other bank, allowing flexible adaptation to varying translation demands while optimizing power consumption by avoiding static allocation of large buffer capacity.
3Adaptability or versatility
If translation entries are transferred between storage banks based on occupancy levels, then flexibility and performance are improved, but device complexity increases
Solution Approach 1:
The buffering management circuitry implements dynamic transfer of translation entries between the two storage banks based on real-time occupancy levels. This dynamic management provides flexibility to adapt to varying translation demands while maintaining relatively simple control logic that monitors bank occupancy and triggers transfers when thresholds are reached.
Data Source
AI summary
Memory address translation buffering circuitry is provided comprising a primary storage bank and a secondary storage bank. Storage bank accessing circuitry is provided to perform a parallel lookup of the primary storage bank and the secondary storage bank for virtual to physical address translation entries. Buffering management circuitry is configured to transfer an address translation entry between the primary storage bank and the secondary storage bank dependent upon an occupancy level of at least one of the primary storage bank and secondary storage bank.