Dual Barrier Interconnect Structure for Semiconductor Fabrication
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Solution Overview
Problem
Current semiconductor fabrication techniques, such as single and dual damascene processes, require multiple chemical mechanical planarization steps, which can be inefficient and prone to plasma-induced damage, especially when forming interconnect structures and metal vias.
Innovation Solution
The implementation of a method involving the formation of interconnect structures with a first and second barrier layer, where the first barrier layer is deposited using atomic layer deposition and the second layer using plasma-based deposition, to prevent copper diffusion and minimize plasma-induced damage, while also forming a pad layer over these barriers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple chemical mechanical planarization steps are used in single or dual damascene processes, then interconnect structures and metal vias can be formed, but the process becomes inefficient and prone to plasma-induced damage
Solution Approach 1:
The process is divided into separate etching and planarization stages, allowing each to be optimized independently. The etching process creates the interconnect structures and metal vias, while the planarization process separately addresses surface flatness, eliminating the need for multiple iterative CMP steps
Solution Approach 2:
The etching process is designed to pre-form the interconnect structures and metal vias with appropriate geometry before final planarization. This preliminary structuring allows subsequent planarization to focus only on surface flatness rather than repeated structure formation and flattening cycles
2Manufacturing precision
If multiple chemical mechanical planarization steps are used, then interconnect structures can be formed, but plasma-induced damage increases
Solution Approach 1:
The process separates etching and planarization into distinct stages, reducing the cumulative plasma exposure and associated damage that would occur in multiple iterative CMP cycles. Each stage uses plasma conditions optimized for its specific function rather than repeated generic plasma treatment
Solution Approach 2:
The process rushes through the structure formation phase in a single etching step rather than repeatedly forming and re-planarizing structures. This minimizes the total time and number of plasma exposure events, reducing cumulative plasma-induced damage to the interconnect structures
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the need for multiple chemical mechanical planarization steps and minimizes plasma-induced damage, enhancing the efficiency and reliability of interconnect structure formation in semiconductor devices.
Implementation Method 1
the first barrier layer is deposited using atomic layer deposition
Implementation Method 2
the second layer using plasma-based deposition
Data Source
AI summary
An apparatus includes a plurality of interconnect structures over a substrate, a dielectric layer formed over a top metal line of the plurality of interconnect structures, a first barrier layer on a bottom and sidewalls of an opening in the dielectric layer, wherein the first barrier layer is formed of a first material and has a first thickness, a second barrier layer over the first barrier layer, wherein the second barrier layer is formed of a second material different from the first material and has a second thickness and a pad over the second barrier layer, wherein the pad is formed of a third material.