Dual Barrier Liner Structure for Semiconductor Interconnects
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Solution Overview
Problem
The semiconductor industry faces challenges in forming reliable semiconductor devices at smaller sizes due to increased complexity and difficulty in fabrication processes as feature sizes decrease, leading to issues with resistance-capacitance (RC) delay and metal diffusion, which affect device performance and reliability.
Innovation Solution
The implementation of a dual barrier liner structure, comprising a first barrier liner and a second barrier liner, deposited using atomic layer deposition (ALD) processes, to protect dielectric layers from metal diffusion and enhance the reliability of conductive features by reducing RC delay and maintaining low capacitance, while also providing physical strength and adhesion to the conductive features.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If feature sizes are decreased to increase functional density, then production efficiency is improved and costs are lowered, but fabrication process complexity and difficulty increase
Solution Approach 1:
The patent segments the barrier function into multiple thin liner layers (first barrier liner and second barrier liner) instead of using a single thick barrier layer. This segmentation allows each liner to be deposited by ALD with precise thickness control, reducing overall barrier thickness while maintaining diffusion protection, thereby enabling smaller feature sizes without proportionally increasing process complexity.
Solution Approach 2:
The patent employs composite material structure with different liner materials (e.g., tungsten oxide and tungsten nitride, or tantalum oxide and tantalum nitride) deposited in sequence. This composite approach provides enhanced barrier performance against metal diffusion and electron migration while maintaining thin overall thickness, resolving the contradiction between miniaturization and fabrication complexity.
2Ease of manufacture
If conventional single barrier liner is used, then process simplicity is maintained, but metal diffusion and electron migration occur affecting device reliability
Solution Approach 1:
The barrier function is segmented into two sequential liner deposits, each performed by ALD process. The first liner provides initial barrier protection, and the second liner enhances the barrier against metal diffusion and electron migration. This segmentation improves reliability while maintaining process simplicity through standardized ALD deposition steps.
Solution Approach 2:
The patent uses composite liner materials with different properties (oxide and nitride layers) to provide superior barrier performance against both metal diffusion and electron migration compared to a single material system, thereby improving device reliability while using well-established ALD processes.
3Reliability
If thicker barrier liner is used to prevent metal diffusion, then diffusion protection is improved, but capacitance increases and RC delay worsens
Solution Approach 1:
The barrier function is divided into two thin liner layers deposited sequentially by ALD, achieving sufficient diffusion protection with much thinner total thickness compared to a single thick barrier layer. This segmentation reduces the capacitive effect on underlying conductive features, thereby reducing RC delay while maintaining diffusion protection.
Solution Approach 2:
The patent changes the barrier approach from thickness-based protection to material-composition-based protection, using specific ALD-deposited oxide and nitride liner materials that provide high barrier performance at atomic-level thicknesses, thus reducing capacitance and RC delay while maintaining diffusion protection.
4Productivity
If smaller feature sizes are fabricated, then functional density increases, but metal diffusion and electron migration become more problematic
Solution Approach 1:
The barrier protection is segmented into two thin ALD-deposited liners that conformally coat the conductive features and surrounding dielectric. This segmented approach provides comprehensive barrier coverage against metal diffusion and electron migration at smaller feature sizes where traditional single-layer barriers become too thick and problematic.
Solution Approach 2:
The patent employs composite liner materials (oxide and nitride combinations) that provide synergistic barrier properties against both metal diffusion and electron migration, enabling effective protection at smaller feature sizes where conventional single-material barriers would require excessive thickness and compromise device performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The dual barrier liner structure significantly reduces metal diffusion and electron migration, lowers electrical resistance, and improves the reliability and performance of semiconductor devices by maintaining low capacitance and enhancing the physical strength of conductive features, thereby stabilizing the interconnection structure.
Implementation Method 1
deposited using atomic layer deposition (ALD) processes
Data Source
AI summary
Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a conductive feature in a first dielectric layer. The semiconductor device structure also includes an etching stop layer over the first dielectric layer and a second dielectric layer over the etching stop layer. The semiconductor device structure further includes a conductive via in the etching stop layer and the second dielectric layer. In addition, the semiconductor device structure includes a conductive line over the conductive via. The semiconductor device structure also includes a first barrier liner covering the bottom surface of the conductive line. The semiconductor device structure further includes a second barrier liner surrounding sidewalls of the conductive line and the conductive via. The conductive line and the conductive via are confined in the first barrier liner and the second barrier liner.