Partitioned Dual Bit Line Layout for Lower Memory Array RC
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Solution Overview
Problem
Existing semiconductor memory cell arrays face challenges in reducing resistance and capacitance, which affect operational efficiency and speed.
Innovation Solution
Implementing a memory cell array with a partitioned dual bit line structure, including bridges that electrically connect metal wirings, and a partitioned dual power line structure to separate and reduce resistance and capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a conventional single bit line structure is used, then the layout is simple, but the resistance and capacitance are high which affects operational speed
Solution Approach 1:
The bit line is divided into multiple segments (first bit line segment and second bit line segment) that are separated by cutting portions. This segmentation reduces the capacitance between adjacent bit lines by increasing the distance between them, thereby improving operational speed while managing the structural complexity through modular design
Solution Approach 2:
The patent introduces a third dimension by stacking metal wirings vertically. Multiple bit lines are formed using different metal layers (first metal wiring, second metal wiring, third metal wiring) at different heights, allowing bit lines to be separated in the vertical dimension rather than only in the planar dimension, thus reducing capacitance without excessive planar complexity
2Object-affected harmful factors
If bit lines are spaced further apart to reduce capacitance, then capacitance decreases, but the area occupied increases
Solution Approach 1:
By utilizing vertical stacking of metal layers, the patent reduces capacitance between bit lines without increasing the planar area. Bit lines are separated in the vertical dimension (different metal layers) rather than requiring larger horizontal spacing, thus reducing capacitance while maintaining compact area
Solution Approach 2:
Multiple bit line segments are nested across different metal layers, with each layer containing portions of the bit line structure. This nested arrangement allows efficient use of vertical space to reduce capacitance without proportionally increasing the horizontal area
3Object-affected harmful factors
If metal wirings are extended continuously, then connectivity is maintained, but resistance increases
Solution Approach 1:
The continuous metal wiring is segmented into discrete portions (first portion and second portion separated by cutting portion). This segmentation reduces the overall resistance by eliminating resistive paths through high-capacitance regions while bridges provide selective reconnection to maintain necessary connectivity
Solution Approach 2:
High-resistance or high-capacitance portions of the metal wiring are extracted and removed via cutting portions. The unnecessary continuous path is taken out, and only the essential connections are maintained through bridges, thereby reducing overall resistance while preserving functional connectivity
Data Source
AI summary
An integrated circuit includes is provided. The integrated circuit includes: a plurality of bit lines spaced apart from each other along a first direction and extending in a second direction perpendicular to the first direction through a first sub-array and a second sub-array neighboring the first sub-array in the second direction. Each of the plurality of bit lines includes: a first metal wiring extending in the second direction, the first metal wiring including a first portion and a second portion that is separated from the first portion by a first cutting portion; a third metal wiring extending in the second direction, and at least partially overlapping the first metal wiring along a third direction perpendicular to the first direction and the second direction; and two bridges electrically connecting the first metal wiring to the third metal wiring.