Dual Bit Memory Cell Gate Dielectric Segmentation
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Solution Overview
Problem
As semiconductor memory devices shrink in size, the reduced spacing between dual storage nodes in dual bit memory cells leads to reliability and data retention issues due to charge leakage and programming disturbances, limiting erasing options and increasing power consumption.
Innovation Solution
The method involves forming a gate dielectric layer and central gate electrode on a semiconductor substrate, with independently created first and second memory storage nodes, each comprising a tunnel dielectric layer, charge storage layer, and control gates, allowing for enhanced isolation and Fowler-Nordheim tunneling for erasing, reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If device size is reduced to increase storage capacity, then storage density is improved, but charge leakage between storage nodes increases
Solution Approach 1:
The gate dielectric layer is segmented into two independently formed layers: a first gate dielectric layer formed with the charge storage layer, and a second gate dielectric layer formed separately to provide enhanced isolation. This segmentation allows the gate structure to simultaneously support high storage density while preventing charge leakage between adjacent storage nodes through the additional dielectric barrier.
Solution Approach 2:
The independently formed gate dielectric layer acts as an intermediary barrier between the two storage nodes. This additional dielectric layer is specifically introduced to block charge tunneling and leakage paths that would otherwise occur due to the reduced spacing between storage nodes in high-density configurations.
2Area of moving object
If spacing between storage nodes is decreased to increase capacity, then storage density is improved, but charge leakage through gate structure increases
Solution Approach 1:
The gate dielectric is divided into multiple independently formed layers, with the second gate dielectric layer specifically designed to provide enhanced isolation between closely spaced storage nodes. This segmentation enables the structure to maintain small node spacing for high density while the additional dielectric layer prevents harmful charge leakage.
Solution Approach 2:
The gate structure employs a composite dielectric configuration with at least two different dielectric materials or layers having different electrical properties. This composite structure provides both the necessary capacitance for charge storage and enhanced isolation to prevent charge leakage, allowing close node spacing without sacrificing reliability.
3Productivity
If programming of one storage node is performed, then data is written, but data in the other storage node is disturbed due to wide charge distribution
Solution Approach 1:
The independently formed gate dielectric layer serves as an intermediary barrier that confines charge distribution during programming operations. This additional dielectric layer prevents charge from spreading laterally into adjacent storage nodes, thereby maintaining data integrity in the non-programmed node while allowing rapid programming of the target node.
4Ease of operation
If conventional erasing methods are used, then memory is erased, but power consumption is high
Solution Approach 1:
The independently formed gate dielectric structure enables Fowler-Nordheim tunneling erasing by creating appropriate electric field conditions across the dielectric layers. This parameter change in the erasing mechanism allows for lower power consumption compared to conventional hot carrier erasing methods, as FN tunneling can be achieved with more efficient voltage application across the gate structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances data retention and reliability by preventing charge leakage between storage nodes and enables efficient erasing through Fowler-Nordheim tunneling, reducing power consumption and maintaining data integrity across repeated cycles.
Implementation Method 1
forming a gate dielectric layer... each of the first and second storage nodes comprising a first dielectric layer... enhancing isolation between memory storage nodes
Implementation Method 2
dual bit memory cell devices that can be erased by Fowler-Nordheim (FN) tunneling for less power consumption
Data Source
AI summary
Methods are provided for fabricating a memory device comprising a dual bit memory cell. The method comprises, in accordance with one embodiment of the invention, forming a gate dielectric layer and a central gate electrode overlying the gate dielectric layer at a surface of a semiconductor substrate. First and second memory storage nodes are formed adjacent the sides of the gate dielectric layer, each of the first and second storage nodes comprising a first dielectric layer and a charge storage layer, the first dielectric layer formed independently of the step of forming the gate dielectric layer. A first control gate is formed overlying the first memory storage node and a second control gate is formed overlying the second memory storage node. A conductive layer is deposited and patterned to form a word line coupled to the central gate electrode, the first control gate, and the second control gate.