Dual-bit Memory Trench Isolation Near Bit Line Contacts

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Solution Overview

Problem

Conventional dual-bit flash memory devices experience increased parasitic leakage current as cell size shrinks, leading to higher programming currents and affecting read and verification operations, especially in low power applications like portable electronics.

Innovation Solution

Incorporating trench isolation material near bit line contact areas to prevent current flow between adjacent bit lines, using techniques like LOCOS or STI to form isolation trenches that block leakage currents.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If cell size is shrunk to increase storage density, then storage capacity per unit area is improved, but parasitic leakage current between bit lines increases

Engineering Contradiction:
Improvestorage capacity per unit areaVSAvoidparasitic leakage current
Core Design Contradiction:
Quantity of substanceVSObject-generated harmful factors

Solution Approach 1:

The patent divides the continuous substrate into isolated regions by introducing trench isolation structures between adjacent bit lines. This segmentation physically separates the bit lines, preventing parasitic leakage current while maintaining high storage density through compact cell design.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The trench isolation material acts as an intermediary barrier between adjacent bit lines. This intermediate structure blocks the harmful leakage current path without interfering with the normal operation of the memory cells, effectively mediating between the need for high density and low leakage.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Object-generated harmful factors

If trench isolation material is added to reduce leakage current, then parasitic leakage current is reduced, but device complexity and manufacturing steps increase

Engineering Contradiction:
Improveparasitic leakage currentVSAvoiddevice complexity
Core Design Contradiction:
Object-generated harmful factorsVSDevice complexity

Solution Approach 1:

The trench isolation structure is merged with the existing bit line contact formation process. The same etching and filling steps used to create contact holes are utilized to form the isolation trenches, combining two functions into a single integrated process sequence.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The trench isolation structure serves multiple functions simultaneously: it provides electrical isolation between bit lines, acts as a mechanical support structure, and defines the lateral boundaries of the active regions. This multi-functionality reduces the need for additional dedicated isolation structures.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Productivity

If trench isolation material is added to reduce leakage current, then programming efficiency is improved, but manufacturing cost and process steps increase

Engineering Contradiction:
Improveprogramming efficiencyVSAvoidmanufacturing cost
Core Design Contradiction:
ProductivityVSEase of manufacture

Solution Approach 1:

The trench isolation structures are formed preliminarily during the early stages of device fabrication, before the final memory cell programming operations. This preliminary action ensures that the isolation structures are already in place to prevent leakage during subsequent programming cycles, improving programming efficiency without requiring post-fabrication modifications.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS7948052B2Dual-bit memory device having trench isolation material disposed near bit line contact areas
Publication Date: 2011.05.24 INFINEON TECHNOLOGIES LLC
  • US7948052B2 patent drawing
  • US7948052B2 patent drawing
  • US7948052B2 patent drawing

AI summary

A dual-bit memory device is provided which includes trench isolation material disposed near bit line contact areas. For example, in one implementation a semiconductor memory device is provided in which each memory cell can store two bits of information. The memory device comprises a substrate, first and second buried bit lines in the substrate, a first bit line contact on the first buried bit line, a second bit line contact on the second buried bit line, and an insulator region disposed in the substrate between the first buried bit line and the second buried bit line. The insulator region prevents a current from flowing between the first buried bit line and the second buried bit line.