Dual Bit Line Spacer Layout for Dense Memory Contact Margins
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Solution Overview
Problem
The integration of semiconductor memory devices is limited by the challenges in reducing line widths and achieving effective exposure techniques, which hinder further miniaturization and increased density.
Innovation Solution
The use of separate upper and lower bit line spacers with distinct thicknesses, where the lower spacer is defined by a first thickness and the upper spacer by a second thickness less than the first, allowing for independent control of critical dimensions and reduced parasitic capacitance, enabling higher integration and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If line widths are reduced to increase integration, then device density increases, but exposure techniques become insufficient and manufacturing precision deteriorates
Solution Approach 1:
The bit line spacer is divided into two separate structures: a lower spacer and an upper spacer. This segmentation allows each spacer to be independently formed with optimized dimensions, enabling precise control of critical dimensions without being constrained by single-step exposure limitations. The lower spacer has a first thickness and the upper spacer has a second thickness, allowing independent optimization for different functional requirements.
Solution Approach 2:
The invention transitions from a single-dimensional spacer structure to a multi-dimensional structure by stacking spacers vertically at different heights. The lower spacer is positioned at a lower height and the upper spacer at a higher height, creating a three-dimensional arrangement that enables independent dimension control in the vertical direction, thereby achieving precise critical dimension control without being limited by planar exposure resolution.
2Device complexity
If single thickness spacers are used, then manufacturing process is simple, but critical dimension control and parasitic capacitance reduction are insufficient
Solution Approach 1:
The spacer structure is segmented into lower and upper portions with different thicknesses. The lower spacer provides a first thickness optimized for certain critical dimensions, while the upper spacer provides a second thickness optimized for other dimensions. This segmentation enables precise control of different critical dimensions that would be impossible with a uniform thickness spacer.
Solution Approach 2:
Different regions of the spacer structure are assigned different thickness properties: the lower spacer region has a first thickness and the upper spacer region has a second thickness. This local quality variation allows each region to be optimized for its specific function, achieving superior critical dimension control and parasitic capacitance reduction while maintaining overall structural integrity.
3Ease of manufacture
If thicker spacers are used uniformly, then manufacturing is easier, but parasitic capacitance increases and integration density decreases
Solution Approach 1:
The spacer structure implements local quality variation by positioning a thinner upper spacer above a lower spacer with different thickness. This allows the upper region to have reduced thickness for minimizing parasitic capacitance between bit lines and storage nodes, while the lower region maintains adequate thickness for structural support and alignment tolerance, achieving both low parasitic capacitance and ease of manufacture.
Solution Approach 2:
The lower spacer acts as an intermediary structure between the substrate and the upper spacer. It provides a foundation that enables the upper spacer to be positioned at an optimized height and thickness, mediating between the requirements for structural stability and parasitic capacitance reduction. This intermediary structure allows the upper spacer to be thinner without compromising overall device reliability.
Data Source
AI summary
A volatile memory device can include a bit line structure having a vertical side wall. A lower spacer can be on a lower portion of the vertical side wall, where the lower spacer can be defined by a first thickness from the vertical side wall to an outer side wall of the lower spacer. An upper spacer can be on an upper portion of the vertical side wall above the lower portion, where the upper spacer can be defined by a second thickness that is less than the first thickness, the upper spacer exposing an uppermost portion of the outer side wall of the lower spacer.