Dual-Block Computing-in-Memory With Shared ADC for MAC Operations
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Solution Overview
Problem
Conventional computer systems face inefficiencies due to separate data storage and processing, leading to increased time and energy consumption from data round-trips between processor and memory, which is exacerbated in AI applications like Convolutional Neural Networks.
Innovation Solution
A computing-in-memory (CIM) device with two memory blocks and a controlling circuit that enables simultaneous writing and calculating modes, allowing shared use of an ADC array for MAC operations, reducing resource waste and enhancing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If data storage and processing are separated in conventional architectures, then data can be stored in memory and processed by the processor, but data round-trip between memory and processor increases time and energy consumption
Solution Approach 1:
The patent merges data storage and processing functions by implementing CIM units within the memory array structure. Each memory cell is equipped with computing capabilities, allowing MAC operations to be performed directly where data is stored. This eliminates the need for data to travel between memory and processor, simultaneously reducing energy consumption and computation latency.
Solution Approach 2:
The patent introduces a new architectural dimension by integrating computing units within the memory array's row and column structure. Instead of separate processing units accessing memory, the memory array itself becomes a computing substrate, transforming the traditional von Neumann architecture into an in-memory computing system that operates in a different structural dimension.
2Adaptability or versatility
If a single ADC array is shared between first and second memory blocks, then resource utilization is improved, but potential access conflicts may occur
Solution Approach 1:
The patent implements a universal ADC array that serves both the first and second memory blocks. This single ADC array is designed to handle analog-to-digital conversion for MAC operation results from either memory block, improving resource utilization by eliminating redundant ADC arrays while maintaining full functionality for both computing units.
Solution Approach 2:
The controlling circuit is designed to预先 allocate and manage ADC array access rights before conflicts occur. By controlling the timing and sequencing of MAC operations from the first and second memory blocks, the system preemptively prevents access conflicts, ensuring that only one memory block uses the ADC array at a time through coordinated scheduling.
3Productivity
If two memory blocks are used for parallel MAC operations, then computing speed is improved, but hardware resources increase
Solution Approach 1:
The patent segments the memory system into two distinct memory blocks, each containing CIM units capable of independent MAC operations. This segmentation enables parallel computing where both blocks can perform operations simultaneously, doubling the effective computing throughput while sharing common resources like the ADC array and control logic to mitigate hardware resource increases.
Solution Approach 2:
While dividing memory into two blocks for parallel processing, the patent merges shared resources including a single ADC array, common controlling circuitry, and shared data pathways. This combination approach allows two memory blocks to operate in parallel without proportionally increasing all hardware resources, as critical components are shared between both blocks.
Data Source
AI summary
This disclosure presents a computing-in-memory (CIM) device, including two CIM blocks. These two blocks are connected to the same read bit lines and share an analog-to-digital converter array. The two CIM blocks can perform writing operations simultaneously in one mode. In this case, one block stores a weight matrix, while the other stores the transpose of the weight matrix. In another mode, one CIM block performs the write operation while the other conducts a multiply-accumulate operation. This CIM device can be applied in both inference and training phases.