Dual Board-on-Chip IC Packaging for High-Speed Signal Integrity
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Solution Overview
Problem
Current integrated circuit packaging technologies face challenges in accommodating high-speed devices exceeding one TeraHertz, with limitations in cooling, reliability, and cost-effectiveness, while also struggling with increasing complexity and potential errors in manufacturing, especially in achieving smaller footprints and more robust packages.
Innovation Solution
The implementation of a dual board-on-chip structure with a first integrated circuit die mounted over a substrate and a second integrated circuit die mounted under an interposer, connected via internal interconnects and encapsulated for enhanced connection density and robustness, using substrate and interposer cavities for improved assembly and encapsulation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If current packaging technologies are used for high-speed devices exceeding one TeraHertz, then device speed is improved, but cooling capability and reliability deteriorate
Solution Approach 1:
The packaging system is divided into multiple substrates (first substrate, second substrate, third substrate) with distinct functional regions. Each substrate handles specific tasks: the first substrate contains the high-speed device, the second substrate provides cooling functionality with heat sinks, and the third substrate serves as an interconnect layer. This segmentation allows optimization of each component for its specific function while maintaining overall system reliability.
Solution Approach 2:
The patent transitions from planar packaging to a three-dimensional stacked architecture where substrates are arranged vertically. The first substrate is mounted on the second substrate, which is in turn mounted on the third substrate, creating a multi-layer configuration. This vertical arrangement increases connection density and allows heat dissipation pathways to extend in the vertical dimension, improving cooling capability for high-speed devices.
2Manufacturing precision
If automation is implemented to achieve smaller footprints and acceptable yield, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
The complex packaging structure is divided into modular substrate assemblies that can be manufactured and tested independently before final assembly. Each substrate can be produced using standardized automated processes, and the modular design allows for easier integration and quality control, reducing the complexity burden on the overall manufacturing system.
Solution Approach 2:
The patent employs a nested configuration where the first substrate with the high-speed device is mounted within the structure of the second substrate, which itself is mounted on the third substrate. This nesting arrangement achieves compact footprint dimensions while maintaining clear hierarchical assembly steps that can be automated, as each layer is integrated onto the previous layer in a systematic sequence.
3Reliability
If connection density is increased for robust packages, then reliability is improved, but parasitic inductance increases affecting high-frequency transmission
Solution Approach 1:
The patent utilizes vertical stacking of substrates to achieve high connection density in the vertical dimension rather than increasing horizontal trace density. This three-dimensional interconnection approach reduces the length of current paths and minimizes loop areas, thereby reducing parasitic inductance while maintaining robust mechanical connections between layers.
Solution Approach 2:
The second substrate acts as an intermediary layer between the first substrate (containing the high-speed device) and the third substrate (providing external connections). This intermediate substrate provides dedicated signal routing paths and grounding layers that minimize inductive coupling between signal traces, allowing high connection density without proportionally increasing parasitic inductance.
Data Source
AI summary
A method of manufacture of an integrated circuit packaging system includes: providing a first board-on-chip-structure having a first integrated circuit die mounted over a substrate and the substrate having a substrate cavity; mounting a second board-on-chip-structure over the first board-on-chip-structure, the second board-on-chip-structure having a second integrated circuit die mounted under an interposer and the interposer having an interposer cavity; connecting the first board-on-chip-structure to the second board-on-chip-structure with an internal interconnect; and encapsulating the first board-on-chip-structure, the second board-on-chip-structure, and the internal interconnect with an encapsulation.