Dual Boost Memory Circuit for Low Voltage Write Reliability
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Solution Overview
Problem
Conventional memory circuitry faces challenges in maintaining writeability at low periphery voltages, leading to reverse write failures and increased ground bounce, which limits the minimum operating voltage of System on a Chip (SoC) devices and degrades write margin.
Innovation Solution
The implementation of a dual boost scheme, including a dual boost reverse write suppress scheme and write assist scheme, which selectively applies negative and positive boosted voltages to the gate of write drivers based on the data to be written, using complementary boost generators and write drivers to enhance write operations at low periphery voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If periphery voltage is reduced to save power, then power consumption is reduced, but write ability degrades significantly
Solution Approach 1:
The patent applies preliminary action by pre-charging the bitline to a voltage higher than the conventional voltage before the write operation. This pre-charged bitline provides sufficient voltage headroom to overcome the weakened write driver strength at low periphery voltages, enabling reliable write operations while maintaining low operating voltage and reducing power consumption.
2Use of energy by moving object
If periphery voltage is reduced, then power savings are achieved, but ground bounce decreases leading to increased assist requirement
Solution Approach 1:
The patent pre-charges the bitline to a higher voltage before the write operation, which compensates for the reduced ground bounce effect at low periphery voltages. This preliminary voltage preparation ensures that the bitline maintains sufficient voltage level throughout the write operation, reducing the need for additional assist voltage and enabling power savings.
3Use of energy by moving object
If high split between core voltage and periphery voltage is used, then power efficiency is improved, but reverse writes occur deteriorating write margin
Solution Approach 1:
The patent pre-charges the bitline to a voltage higher than the periphery voltage before the write operation. This preliminary action ensures that even with a high voltage split between core and periphery, the bitline maintains sufficient voltage headroom to prevent reverse writes and maintain adequate write margin, while still allowing power efficient operation at low periphery voltage.
Solution Approach 2:
The patent changes the voltage parameter of the bitline dynamically by pre-charging it to a higher voltage level before the write operation. This parameter change allows the system to maintain a high split between core and periphery voltage for power efficiency while ensuring the bitline voltage remains sufficient to prevent reverse writes and maintain write margin.
Data Source
AI summary
Various implementations described herein are directed to a device having a memory cell coupled to complementary bitlines. The memory cell may store at least one data bit value associated with complementary bitline signals received via the complementary bitlines. The device may include a pair of write drivers coupled to the memory cell via the complementary bitlines. The pair of write drivers may be arranged to provide the complementary bitline signals to the memory cell based on complementary boost signals. The device may include a pair of complementary boost generators coupled to corresponding gates of the pair of write drivers. The pair of complementary boost generators may be arranged to selectively provide the complementary boost signals to the corresponding gates of the pair of write drivers based on the at least one data bit value.