Dual Boot Memory Swap Mechanism for Zero-Downtime Firmware Updates
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Solution Overview
Problem
Existing panel swap mechanisms in microcontrollers require device resets, leading to significant latency and downtime, especially in time-sensitive applications like switched mode power supplies and motor controllers, where continuous execution and peripheral operation are crucial during firmware updates.
Innovation Solution
A dual boot panel swap mechanism within a microcontroller allows for switching between code images without resetting the device, using a dedicated instruction (BOOTSWP) to swap active and inactive memory areas, enabling seamless updates with minimal disruption to exception timing and continuous operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a device reset is performed to switch between code images, then the code image switching is reliable, but the latency increases significantly and continuous execution is interrupted
Solution Approach 1:
The system prepares two code images in advance (active and inactive memory areas) so that when switching is needed, the new image is already loaded and ready to execute immediately, eliminating the need for time-consuming reset sequences
Solution Approach 2:
A dedicated BOOTSWP instruction acts as an intermediary mechanism that facilitates smooth transition between code images by coordinating the switch at the instruction level, avoiding the need for full device reset while ensuring reliable switching
2Reliability
If a device reset is performed to update firmware, then the update is complete, but the application execution and peripheral operation are halted
Solution Approach 1:
The system maintains continuous execution by allowing the application to run from the active memory area while firmware updates are performed in the inactive memory area, and switching occurs seamlessly without interrupting the overall system operation
Solution Approach 2:
The firmware update is prepared in advance in the inactive memory area while the system continues to operate normally from the active area, ensuring that the update is complete and ready before switching occurs
3Adaptability or versatility
If traditional panel swap mechanism is used, then code image switching is achieved, but device reset is required causing downtime
Solution Approach 1:
The patent replaces the mechanical reset-based switching mechanism with a software-based instruction (BOOTSWP) that operates at the CPU level, substituting a slow hardware reset sequence with a fast software command that achieves the same goal without the downtime
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AI summary
A central processing unit with dual boot capabilities is disclosed comprising an instruction memory further comprising a first and second memory area which are configured to be individually programmable, wherein first and second memory area can be assigned to an active memory from which instructions are executed and an inactive memory, respectively. The instruction set for the central processing unit comprises a dedicated instruction that allows to perform a swap from the an active memory area to an inactive memory area, wherein the swap is performed by executing the dedicated instruction in the active memory followed by a program flow change instruction in the active memory, whereupon the inactive memory becomes the new active memory and the active memory becomes the new inactive memory and execution of instructions continues in the new active memory.