Dual Bootstrap PWM Driver for MOSFET Mismatch Correction
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Solution Overview
Problem
Traditional open-loop PWM amplifiers exhibit high non-linearity due to mismatches between high-side and low-side drivers, leading to increased total harmonic distortion and in-band noise.
Innovation Solution
A driver system comprising two n-type field-effect transistors and capacitors that track and correct for resistance mismatches between the transistors, implemented in an open-loop PWM driver stage with high-side and low-side bootstrap capacitors to maintain matched gate-to-source voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If traditional open-loop PWM amplifiers are used, then device complexity is reduced, but non-linearity increases due to mismatch between high-side and low-side drivers
Solution Approach 1:
The patent introduces a feedback mechanism where the output signal is fed back to the gates of the high-side and low-side drivers through separate feedback paths. This allows the drivers to automatically adjust their gate-to-source voltages to compensate for mismatches, thereby reducing non-linearity and improving linearity without requiring complex external matching circuits
Solution Approach 2:
The patent dynamically adjusts the gate-to-source voltages of the high-side and low-side drivers based on the output signal level. By changing the voltage parameters in response to operating conditions, the system compensates for mismatches between drivers and maintains consistent linearity across different signal levels
2Loss of energy
If open-loop PWM amplifiers are used, then power efficiency is improved, but total harmonic distortion increases due to driver mismatch
Solution Approach 1:
The feedback paths enable the high-side and low-side drivers to sense output signal imbalances and automatically correct for mismatches by adjusting their respective gate voltages. This reduces total harmonic distortion caused by driver mismatch while preserving the power efficiency benefits of open-loop operation
Solution Approach 2:
The drivers perform self-correction by using the output signal itself to adjust their operating parameters. The feedback mechanism allows each driver to automatically compensate for its own mismatches without requiring external intervention or complex control circuits, thereby reducing THD while maintaining simplicity
3Device complexity
If open-loop PWM amplifiers are used, then device simplicity is maintained, but in-band noise increases due to non-linearity
Solution Approach 1:
The feedback mechanism reduces non-linearity by automatically balancing the gate-to-source voltages of the high-side and low-side drivers. By minimizing driver mismatch through feedback, the system reduces the generation of in-band noise while maintaining the simple open-loop driver configuration
Solution Approach 2:
The feedback paths act as intermediaries that transfer information about output imbalances back to the drivers. This intermediary mechanism enables the simple driver configuration to achieve better linearity and lower in-band noise by using the feedback information to make real-time adjustments
Data Source
AI summary
A driver system may include a first n-type field-effect transistor coupled at its non-gate terminals between an output of the driver system and a first terminal of a supply voltage and configured to drive the output when the first n-type field-effect transistor is activated, a second n-type field-effect transistor coupled at its non-gate terminals between an output of the driver system and a second terminal of the supply voltage and configured to drive the output when the second n-type field-effect transistor is activated, a high-side capacitor coupled to the output of the driver system, and a low-side capacitor coupled to the second terminal of the supply voltage, wherein the high-side capacitor and the low-side capacitor are configured to track and correct for mismatches between a first resistance of the first n-type field-effect transistor and a second resistance of the second n-type field-effect transistor.