Dual-box location-based on-chip variation timing pessimism reduction
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Solution Overview
Problem
Current static timing analysis (STA) techniques in integrated circuit (IC) design are overly pessimistic due to assumptions that introduce significant timing pessimism, especially with the increasing complexity of designs involving multiple voltage domains and spatial variations, leading to difficulties in achieving stringent timing constraints.
Innovation Solution
Advanced on-chip variation (AOCV) techniques such as dual-box location-based (DBLOCV) and advanced location-based (ALOCV) models, which involve forming backward and forward bounding boxes to calculate derate values based on actual cell locations, reducing pessimism by eliminating clock re-convergence pessimism and non-critical side paths, and dual-bitmap voltage domain aware (DBVOCV) analysis to identify and eliminate non-sharing voltage domains.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If a single bounding box is used for timing path analysis, then the analysis is simpler to perform, but timing pessimism increases significantly
Solution Approach 1:
The patent divides the single bounding box into multiple sub-bounding boxes (first sub-bounding box for launch path, second sub-bounding box for capture path). This segmentation allows for more precise location-based derating by calculating distances from launch and capture cells to their respective sub-bounding boxes, thereby reducing timing pessimism while maintaining analytical tractability.
2Reliability
If all voltage domains are considered in timing analysis, then comprehensive coverage is achieved, but the number of voltage corners increases exponentially
Solution Approach 1:
The patent extracts and identifies shared voltage domains that are common to both launch and capture paths. By separating shared voltage domains from non-shared voltage domains, the method only requires analysis of relevant voltage corner combinations, thereby reducing the exponential growth of voltage corners while maintaining comprehensive timing coverage.
Solution Approach 2:
The patent performs preliminary identification of shared voltage domains before conducting full timing analysis. This preliminary action involves determining which voltage domains are common to both launch and capture paths, allowing the analysis to focus only on necessary voltage corner combinations and avoid unnecessary exponential complexity.
3Reliability
If conservative worst-case delays are used in STA, then timing safety is ensured, but timing margin is reduced
Solution Approach 1:
The patent applies location-based derating using sub-bounding boxes to provide spatially varying timing margins. Instead of applying uniform worst-case derating across the entire chip, the method calculates derating factors based on actual distances from cells to their respective sub-bounding box corners. This local quality approach maintains timing safety for critical paths while preserving timing margin for non-critical paths.
Data Source
AI summary
A dual-box location-based on-chip variation (DBLOCV) can be used in STA to significantly reduce pessimism. The DBLOCV analysis includes forming a backward bounding box and a forward bounding box for a cell of the design. A first intermediate maximum distance from the cell to corners of the backward bounding box can be calculated using the coordinates. A second intermediate maximum distance from the cell to corners of the forward bounding box can be calculated using the coordinates. A derate value can be determined from the derate table using the maximum distance of the first and second intermediate maximum distances. STA can be performed using the derate value. At least one timing report can be generated based on the STA.