Dual Branch Execution in Parallel Compute Arrays
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Solution Overview
Problem
Current data processing architectures struggle with efficiently managing and processing large, complex datasets due to inflexibility and inefficiencies in task processing, particularly in handling branch operations and data dependencies, which can lead to computational bottlenecks and inaccuracies.
Innovation Solution
A highly parallel processing architecture using dual branch execution, where a two-dimensional array of compute elements executes both sides of a branch simultaneously while waiting for a branch decision, promoting data from the taken path and ignoring or removing data from the untaken path, thereby optimizing task processing and minimizing computational overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional sequential branch execution is used, then device complexity is reduced, but productivity decreases due to computational bottlenecks and waiting time
Solution Approach 1:
The patent executes both sides of a branch instruction in parallel before the branch outcome is known. Compute elements speculatively execute operations for both potential branch targets simultaneously, preparing results in advance. The valid results are then selected after the branch outcome is determined, eliminating the need to wait for branch resolution before executing subsequent operations.
Solution Approach 2:
The patent dynamically selects which compute element results are valid based on the actual branch outcome. Control logic dynamically determines which speculative execution path produced valid results and routes those results to subsequent operations, while invalid results are discarded. This dynamic selection mechanism allows the system to adapt to different execution paths without requiring separate fixed pipelines.
2Productivity
If dual branch execution is implemented, then productivity increases through parallel execution, but device complexity increases due to additional control logic and data management
Solution Approach 1:
The patent divides the processing architecture into multiple independent compute elements that can be assigned to different branch paths. Each compute element operates independently on its assigned branch, and control logic segments the validation and selection process by examining branch outcome bits to determine which compute element results are valid. This segmentation reduces control complexity compared to a monolithic approach.
Solution Approach 2:
The patent introduces control logic as an intermediary that manages the dual branch execution. This intermediary receives branch outcome information, validates results from appropriate compute elements, and routes valid results to subsequent operations. The intermediary abstracts the complexity of managing parallel speculative execution, presenting a simplified interface to the rest of the processing system.
3Loss of time
If both sides of branch are executed simultaneously, then loss of time is reduced by eliminating waiting periods, but loss of energy increases due to executing potentially redundant operations
Solution Approach 1:
The patent performs preliminary speculative execution of both branch paths simultaneously, eliminating the need to wait for branch outcome before executing subsequent operations. While this initially appears to consume more energy, the parallel execution overlaps with branch resolution time, effectively hiding the waiting period and improving overall throughput. The energy cost of redundant computations is offset by the elimination of idle waiting cycles.
Solution Approach 2:
The patent discards results from the incorrect branch path after validation determines which path was taken. Compute elements that executed the wrong branch path have their results discarded, but the compute elements themselves remain active and can be rapidly reassigned to new operations. This discarding mechanism allows the system to recover quickly and minimize the energy waste from redundant computations by keeping the processing infrastructure hot and ready.
4Reliability
If dual branch execution is used, then reliability increases by eliminating race conditions, but device complexity increases due to data validation and promotion mechanisms
Solution Approach 1:
The patent uses branch outcome information as feedback to validate compute element results. After branch execution, the outcome (which path was taken) is fed back to the control logic, which then validates the results from the corresponding compute element and discards results from the other compute element. This feedback mechanism ensures that only valid results proceed to subsequent operations, eliminating race conditions and ensuring data accuracy.
Solution Approach 2:
The control logic acts as an intermediary that manages the validation and promotion of results from dual branch execution. It receives results from multiple compute elements, validates them against the branch outcome, and promotes only the valid results to the result register file. This intermediary layer abstracts the complexity of result validation, providing a clean interface that ensures reliability without exposing the underlying complexity to the rest of the system.
Data Source
AI summary
Techniques for task processing in a highly parallel processing architecture using dual branch execution are disclosed. A two-dimensional array of compute elements is accessed. Each compute element within the array is known to a compiler and is coupled to its neighboring compute elements within the array of compute elements. Control for the array of compute elements is provided on a cycle-by-cycle basis. The control is enabled by a stream of wide, variable length, control words generated by the compiler. The control includes a branch. Two sides of the branch in the array are executed while waiting for a branch decision to be acted upon by control logic. The branch decision is based on computation results in the array. Data produced by a taken branch path is promoted. Results from a side of the branch not indicated by the branch decision are ignored or invalidated.