Dual Buffer Communication Apparatus for SRAM Efficiency
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Solution Overview
Problem
In high-speed packet communication, the limited memory size of SRAMs used as network buffers restricts the allocation of sufficient buffer space, leading to inefficient use of SRAM for new sending processes due to the need to wait for acknowledgments, causing a deterioration in communication speed.
Innovation Solution
A communication apparatus and method that utilize both SRAM and DRAM as dual network buffers, where data is transferred to both high-speed SRAM and normal DRAM buffers concurrently, allowing the SRAM buffer to be released after sending while the DRAM buffer holds data for potential retransmissions until an acknowledgment is received.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data is retained in SRAM buffer until acknowledgment is received, then communication reliability is ensured, but SRAM buffer space is exhausted and communication speed deteriorates
Solution Approach 1:
The patent divides the buffer management into two separate memory systems: SRAM for high-speed temporary buffering and DRAM for reliable data retention. This segmentation allows each memory type to be optimized for its specific function - SRAM for speed and DRAM for reliability, resolving the contradiction between communication speed and reliability
Solution Approach 2:
The patent introduces DRAM as an intermediary buffer between SRAM and the transmission protocol. When SRAM buffer space is needed for new high-speed transmissions, data can be temporarily moved to or retained in DRAM, which serves as a mediator that maintains communication reliability while freeing up SRAM space for continued high-speed operation
2Productivity
If SRAM memory size is increased to provide sufficient buffer space, then high-speed communication efficiency is improved, but cost and chip area increase
Solution Approach 1:
The patent segments the buffer storage function between two different memory types - SRAM for the high-speed access path and DRAM for additional buffer capacity. This allows the system to achieve sufficient total buffer space without requiring a large SRAM, thereby maintaining high-speed communication efficiency while controlling chip area and cost
Solution Approach 2:
The patent effectively creates a copy mechanism where data can be transferred from SRAM to DRAM when buffer space is needed. This copying approach allows the system to maintain data availability for retransmission while freeing up SRAM space, achieving sufficient buffer capacity without proportionally increasing SRAM size
Data Source
AI summary
A communication apparatus includes the first memory unit which stores data to be a sending target to another communication apparatus and the second memory unit accessible at higher speed than the first memory unit, and transfers the sending target data to the second memory unit concurrently with transfer of the data to the first memory unit. The communication apparatus sends the sending target data from the second memory unit to the other communication apparatus and discards the data from the second memory unit after that sending and before receiving a response to the data from the other communication apparatus. When resending the data, resending processing to the other communication apparatus is performed based on the data transferred to the first memory unit.