Dual-Buffer Mechanism for Consistent Delay in Variable Rate Streams
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Solution Overview
Problem
The existing delay mechanisms in WCDMA receivers face challenges in imposing a consistent delay on information sets due to variable information rates from frame to frame, requiring complex control circuitry that increases cost and complexity.
Innovation Solution
A dual-buffer system is implemented, where each buffer operates for a fixed duration of 256 chip times, ensuring that information sets are stored and outputted at consistent rates without needing complex control circuitry, by alternating between buffers to handle changing information rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a single buffer is used to store information sets with variable information rates, then the delay mechanism can handle variable rates, but it requires complex control circuitry to manage the varying storage and output timing
Solution Approach 1:
The single buffer is divided into two separate buffers (first buffer and second buffer). Each buffer handles a fixed time period (256 chip times), simplifying the control logic for each individual buffer while collectively handling variable information rates across different time periods.
Solution Approach 2:
The system alternates between the first buffer and second buffer in periodic time periods of 256 chip times. During each time period, one buffer is used for storage while the other can be emptied, creating a rhythmic pattern that simplifies control circuitry by establishing predictable timing intervals.
2Adaptability or versatility
If the buffer operates without fixed time periods, then it can flexibly adapt to information rate changes, but it cannot impose a consistent delay on information sets
Solution Approach 1:
The system pre-defines fixed time periods of 256 chip times for buffer operation. This preliminary structuring of time periods allows the system to impose consistent delays on information sets while still adapting to variable information rates by alternating between buffers at these predetermined intervals.
3Manufacturing precision
If complex control circuitry is used to manage variable information rates, then consistent delay can be imposed, but the cost and complexity of the receiver increases
Solution Approach 1:
By segmenting the buffer into two separate buffers with fixed time period assignments, the control circuitry for each buffer becomes simpler and more predictable, reducing overall complexity and cost while maintaining precise delay timing through the alternating operation pattern.
Solution Approach 2:
The dual-buffer system with fixed time periods enables a more self-regulating operation where each buffer independently manages its own timing and storage operations during its designated time period, reducing the need for complex centralized control circuitry.
Data Source
AI summary
A mechanism is disclosed for imposing a delay on a variable rate information stream. A stream of information sets is received, where the stream has a variable information rate that can change from time period to time period. In a first time period, information sets are stored into a first buffer. In a second time period, information sets are stored into a second buffer. Because of the variable information rate, the number of information sets stored into the first and second buffers may differ. After a delay period has elapsed since the beginning of the first time period, the information sets in the first buffer are outputted. After a delay period has elapsed since the beginning of the second time period, the information sets in the second buffer are outputted. In this manner, a consistent delay is imposed on the information sets regardless of the information rate of the stream.