Dual Buffer Backup Mechanism for Flash Memory Data Integrity

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Solution Overview

Problem

Sudden power-offs during write operations in flash memory devices can damage data, leading to performance issues and data loss, as existing technologies fail to effectively prevent or recover from such events.

Innovation Solution

A data storage system with a dual-buffer structure, comprising an MLC block and an SLC block, along with a backup memory block, where the controller determines the optimal buffer for writing data based on size and priority, and writes a portion of the data from the first buffer into the backup block to prevent data loss during power-outs.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If data is written continuously into a single buffer during a write operation, then write speed is improved, but data reliability deteriorates when sudden power-off occurs

Engineering Contradiction:
Improvewrite speedVSAvoiddata reliability
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The patent divides the buffer into multiple segments (first buffer and second buffer) with different retention characteristics. The first buffer provides high-speed write capability while the second buffer ensures data reliability through power-loss protection, resolving the contradiction between write speed and data reliability.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces an intermediary mechanism where the controller manages data transfer between the first buffer and second buffer. When power-off is detected or predicted, the controller transfers critical data from the first buffer to the second buffer, ensuring data reliability without sacrificing normal write performance.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If a backup mechanism is implemented to prevent data loss during power-off, then data reliability is improved, but device complexity increases

Engineering Contradiction:
Improvedata reliabilityVSAvoiddevice complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent merges the backup function with the existing buffer structure by integrating a second buffer into the same memory device. This combined approach provides power-loss protection while minimizing the increase in device complexity through shared physical and control resources.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The controller automatically detects power-off conditions and manages data transfer between buffers without external intervention. The system self-manages the backup process, reducing the need for additional complex control mechanisms outside the normal write operation flow.

Inventive Principle:
Principle #25Self-service

3Reliability

If all data in a buffer is discarded when power-off occurs, then data damage is prevented, but productivity deteriorates due to data loss

Engineering Contradiction:
Improvedata integrityVSAvoidproductivity
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent applies local quality protection by selectively preserving only the most critical data in the second buffer while allowing other data to be discarded. This targeted approach maintains data integrity for essential information while minimizing productivity loss from data discards.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent implements a selective discarding strategy where data in the second buffer is preserved during power-off events, while data in the first buffer may be discarded. This recovery mechanism ensures that critical data is not lost, maintaining productivity by preserving usable data for potential recovery operations.

Inventive Principle:
Principle #34Discarding and recovering

Data Source

PatentUS10592410B2Backup mechanism of writing sequential data to single-level cell buffer and multi-level cell buffer
Publication Date: 2020.03.17 SILICON MOTION INC
  • US10592410B2 patent drawing
  • US10592410B2 patent drawing
  • US10592410B2 patent drawing

AI summary

A data storage device includes a memory device and a controller. The memory device includes a first buffer, a second buffer, and a backup memory block. The first buffer is an MLC block and the second buffer is an SLC block. The controller is coupled to the memory device, receives a write command to write predetermined data in the memory device and determines whether the predetermined data has to be written into different buffers. When the controller determines that the predetermined data has to be written into different buffers, the controller writes a portion of the predetermined data that has been written in one or more predetermined pages of the first buffer into the backup memory block.