Dual-Buffer Memory Control for Neural Network Weight Data
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Solution Overview
Problem
The existing methods for memory control in neural networks, such as CNN operations, face challenges in balancing memory capacity and operation speed, particularly when switching kernels between buffer memory areas, which can lead to increased circuit size and limited processing capacity.
Innovation Solution
The implementation of a dual-buffer memory system where two areas can be accessed simultaneously for kernel transfer, allowing parallel reading and writing operations, thereby reducing memory requirements while maintaining or increasing operation speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If kernels are switched between buffer memory areas in traditional double buffer method, then operation speed is improved, but memory usage increases
Solution Approach 1:
The patent segments the buffer memory into multiple areas (first buffer area, second buffer area, third buffer area) and implements different buffer methods (double buffer method, single buffer method, frame buffer method) in different segments. This allows the system to use double buffer method only where needed for speed-critical operations while using more memory-efficient methods elsewhere, thereby improving operation speed without proportionally increasing overall memory usage.
Solution Approach 2:
The patent dynamically switches between different buffer methods (double buffer, single buffer, frame buffer) based on the processing requirements of different loops. The control unit selects the appropriate buffer method for each loop, allowing the system to adapt memory usage to actual processing needs, thus improving speed when necessary while reducing memory usage when possible.
2Quantity of substance
If dual-buffer memory system with parallel access is implemented, then memory requirements are reduced, but device complexity increases
Solution Approach 1:
The patent creates a universal buffer memory system that can operate in multiple modes (double buffer, single buffer, frame buffer methods) using the same physical memory structure. The control unit selects which buffer method to apply based on processing requirements, making the memory system multi-functional. This reduces the need for separate dedicated memory structures for each buffer method, thereby reducing overall memory requirements while managing complexity through software/control logic.
3Productivity
If traditional memory control methods are used, then device complexity is kept low, but productivity is limited
Solution Approach 1:
The patent implements dynamic buffer method selection where the control unit chooses between double buffer, single buffer, and frame buffer methods based on the specific processing requirements of each loop. This dynamic adaptation allows the system to optimize processing capacity for different workloads without requiring a permanently complex control structure, thereby improving productivity while keeping control complexity manageable through conditional logic.
Solution Approach 2:
The patent applies different buffer methods to different loops or processing stages based on their specific requirements. Some loops may benefit from double buffer method for speed, while others can use more efficient single buffer method. This localized optimization improves overall processing capacity without uniformly increasing control complexity across the entire system.
Data Source
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AI summary
There is provided with an information processing apparatus. A control means (108) controls writing of weight data to a first memory (103) and a second memory (104), and controls readout of the weight data from the first memory (103) and the second memory (104). The control means (108) further switches an operation between a first operation in which a processing means (106) reads out first weight data from the first memory (103) and performs the convolution operation processing using the first weight data while the processing means (106) writes second weight data to the second memory (104) in parallel, and a second operation in which the processing means (106) reads out the first weight data from both the first memory (103) and the second memory (104) and performs the convolution operation processing using the first weight data.