Dual Buffer Memory System Reducing Data Transmission Time
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Solution Overview
Problem
Current memory systems face performance limitations due to long data transmission times between flash memory and buffers, which are exacerbated when writing data corresponding to multiple buffer capacities, leading to increased chip areas and manufacturing challenges when attempting to increase data bus widths or operating frequencies.
Innovation Solution
A dual buffer memory system that employs a dual buffering scheme, where one buffer interacts with the flash memory while the other interacts with the host, using selection circuits to manage data and control signals, thereby reducing data transmission times and improving system performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If data bus width is increased to reduce data transmission time, then data transmission time is reduced, but chip area is significantly increased
Solution Approach 1:
The invention divides the buffer into multiple segments (first buffer and second buffer) and processes data in parallel through multiple flash memory blocks. This segmentation allows data transmission to occur simultaneously across multiple paths, reducing the effective transmission time without requiring an increase in the width of individual data buses, thereby avoiding the chip area penalty associated with wider buses.
Solution Approach 2:
The invention transitions from a single-buffer sequential processing model to a multi-buffer parallel processing model, adding a temporal and operational dimension to data transmission. By enabling simultaneous read operations from one buffer while another buffer is being written to, the system achieves faster effective transmission rates without increasing physical data bus width or chip area.
2Loss of time
If operating frequency is increased to reduce data transmission time, then data transmission time is reduced, but manufacturing becomes more difficult
Solution Approach 1:
The invention segments the buffer and flash memory operations into parallel independent units (first buffer/first flash block, second buffer/second flash block) that can operate simultaneously at standard frequencies. This parallelism achieves the effect of higher throughput without actually increasing the operating frequency, thereby avoiding the manufacturing difficulties associated with high-frequency operation.
Solution Approach 2:
The invention ensures continuous useful action by enabling overlapping operations: while data is being read from one buffer to the host, another buffer is simultaneously being written to from the host, and flash memory blocks are being programmed in parallel. This continuous parallel operation maximizes throughput at standard operating frequencies, avoiding the need for frequency increases that would complicate manufacturing.
3Device complexity
If single buffer is used to simplify system structure, then device complexity is reduced, but data transmission time increases when writing multiple buffer capacities
Solution Approach 1:
The invention divides the buffer into two separate buffers and the flash memory into multiple blocks, creating parallel processing paths. This segmentation enables simultaneous read and write operations across different buffer-flash block pairs, significantly reducing data transmission time for large data sets while maintaining relatively simple control logic through the use of selection circuits.
Solution Approach 2:
The dual buffer system provides multi-functionality by enabling simultaneous execution of different operations: one buffer can be used for reading data to the host while another buffer is used for writing data from the host, and flash memory blocks can be simultaneously programmed. This universal capability to handle multiple operations in parallel reduces transmission time without requiring complex dedicated control mechanisms for each operation type.
Data Source
AI summary
A dual buffer memory system capable of improving system performance by reducing a data transmission time and a control method thereof are provided. The dual buffer memory system includes a flash memory block and a plurality of buffers. The dual buffer memory system uses a dual buffering scheme in which one buffer among the plurality of buffers interacts with the flash memory block and simultaneously a different buffer among the plurality of buffers interacts with a host. Therefore, it is possible to reduce a data transmission time between the flash memory and the host, thereby improving system performance.