Dual Buffer Memory Test Apparatus for High-Speed Fail Data Writing
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Solution Overview
Problem
Existing memory test apparatuses face inefficiencies in writing fail data to address fail memory due to the slow speed of the read-modify-write process, especially when testing at high speeds, and require a large number of address fail memory sections, leading to a costly and bulky setup.
Innovation Solution
A test apparatus with a dual buffering system and a control section that switches data between buffers to optimize the writing process, using a read-modify-write process only when necessary, and employing a burst write process in secondary buffers to enhance speed without increasing the number of address fail memory sections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a read-modify-write process is used to write fail data to the AFM, then data accuracy is maintained, but writing speed becomes extremely slow
Solution Approach 1:
The system divides the AFM into multiple banks (e.g., 4 banks of 1M bits each) and uses multiple buffer sections (first buffer, second buffer, third buffer) to segment the data writing process. This allows parallel processing of different data portions, maintaining accuracy while improving overall writing speed.
Solution Approach 2:
The system performs preliminary buffering of fail data and address data in the first buffer section before writing to the AFM. The control section prepares data in advance and uses the second buffer section to hold data while the read-modify-write process occurs, preventing speed bottlenecks from affecting the testing process.
Solution Approach 3:
Multiple buffer sections act as intermediaries between the high-speed testing process and the slow read-modify-write process. The buffers absorb the speed mismatch, allowing the testing to proceed at high speed while data is gradually transferred to the AFM through the buffering system.
2Speed
If multiple AFMs are arranged in parallel to increase writing speed, then writing speed improves, but the apparatus becomes large and costly
Solution Approach 1:
Instead of using multiple complete AFMs, the system segments a single AFM into multiple banks and uses multiple buffer sections to manage data flow. This achieves parallel-like writing speed improvement while keeping the total memory capacity and apparatus size manageable.
Solution Approach 2:
The system adds the time dimension to the writing process by using multiple buffer sections that can operate at different stages of the read-modify-write cycle. This allows overlapping of data preparation, transfer, and writing operations, effectively increasing writing speed without adding proportional hardware capacity.
Data Source
AI summary
A test apparatus including a first buffer section and a second buffer section that each buffers fail data and address data; an address fail memory section that writes the fail data buffered in the first buffer section to an address of an internal memory indicated by the address data corresponding to the fail data, using an RMW process; and a control section that, in a state in which the fail data and address data output from the testing section are supplied to the first buffer section, when unused capacity of the first buffer section becomes less than or equal to a predetermined first threshold value, supplies the fail data and address data output from the testing section to the second buffer section instead of to the first buffer section.