Dual Input Buffer Layout for High-Speed NAND I/O With Lower Idle Power
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Solution Overview
Problem
The challenge of increasing I/O speed in NAND memory devices leads to higher static power consumption during idle cycles, necessitating a solution that balances performance with power efficiency.
Innovation Solution
Implementing a dual-buffer system with a low speed buffer for command/address signals and a high speed buffer for data signals, optimizing power consumption by enabling the low speed buffer during idle cycles and the high speed buffer during data input cycles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If I/O speed is increased to improve performance, then data transmission speed is improved, but static power consumption during idle cycles increases
Solution Approach 1:
The patent divides the buffer system into two separate buffers: a high-speed buffer for data signals and a low-speed buffer for command/address signals. This segmentation allows the high-speed buffer to be disabled during idle cycles when only command signals are present, thereby reducing static power consumption while maintaining high I/O performance during active data transfer operations.
Solution Approach 2:
The patent implements dynamic buffer enabling/disabling based on operational mode. The high-speed buffer is enabled only during data input cycles and disabled during idle cycles or command-only operations, while the low-speed buffer remains active to handle command and address signals. This dynamic configuration optimizes power consumption according to actual operational needs.
2Speed
If a single high-speed buffer is used for all signals, then data transmission speed is improved, but power consumption increases
Solution Approach 1:
The patent applies different quality characteristics to different signal paths by routing data signals through a high-speed buffer optimized for fast data transfer, while command and address signals are routed through a low-speed buffer optimized for power efficiency. This local quality differentiation ensures that high speed is provided only where necessary (data paths) while reducing power consumption in control paths.
Solution Approach 2:
The patent segments the signal handling into two distinct pathways: one for data signals using a high-speed buffer and another for command/address signals using a low-speed buffer. This segmentation allows independent optimization of each pathway's power consumption characteristics based on its specific performance requirements.
3Use of energy by stationary object
If a dual-buffer system is implemented to reduce power consumption, then power efficiency is improved, but device complexity increases
Solution Approach 1:
The low-speed buffer serves multiple functions: it handles command signals during idle cycles, manages address signals during read/write operations, and can interface with the I/O component during mode transitions. This multi-functionality reduces the need for additional dedicated buffers, thereby limiting the increase in device complexity while achieving power efficiency goals.
Data Source
AI summary
A non-volatile memory device includes input/output (I/O) connections including a first I/O connection and a second I/O connection, a first buffer coupled to the first I/O connection and a second buffer coupled to the second I/O connection, and an input buffer controller coupled to the I/O connections. The input buffer controller is configured to enable the first buffer to buffer a command signal or an address signal when the command signal or the address signal is received from the first I/O connection during a first period of time, enable the second buffer, during a second period of time in a data input cycle, to buffer a data signal at a speed higher than the first buffer, wherein the data signal is received from the second I/O connection in the data input cycle, and disenable the second buffer when the data input cycle is ended. At least part of the second period of time having an overlapping with the first period of time.