Dual-Buffer Input Circuit for High-Speed Noise-Immune Switching
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Solution Overview
Problem
Existing input/output circuits face challenges in achieving high speed operation while maintaining high noise immunity, particularly in nonvolatile memory systems where noise can lead to erroneous signal transitions and errors in data sampling or clock signal reception.
Innovation Solution
The proposed solution involves a circuit with two buffers, one with narrow or zero hysteresis for high speed and another with wide hysteresis for noise immunity, along with an output block that locks and unlocks the final output signal based on transitions from both buffers, ensuring reliable signal processing despite noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a buffer with wide hysteresis is used to improve noise immunity, then noise immunity is improved, but switching speed deteriorates
Solution Approach 1:
The input buffer is divided into two separate buffers: a first buffer with narrow or zero hysteresis for fast switching, and a second buffer with wide hysteresis for noise immunity. Each buffer processes the input signal independently and generates its own output signal, allowing both speed and noise immunity requirements to be met simultaneously through functional segmentation.
2Speed
If a buffer with narrow or zero hysteresis is used to improve switching speed, then switching speed is improved, but noise immunity deteriorates
Solution Approach 1:
The input buffer is divided into two separate buffers: a first buffer with narrow or zero hysteresis for fast switching, and a second buffer with wide hysteresis for noise immunity. Each buffer processes the input signal independently and generates its own output signal, allowing both speed and noise immunity requirements to be met simultaneously through functional segmentation.
3Reliability
If hysteresis is increased to reduce erroneous transitions, then noise immunity is improved, but the number of logic states requiring tracking increases
Solution Approach 1:
The input buffer is divided into two separate buffers: a first buffer with narrow or zero hysteresis for fast switching, and a second buffer with wide hysteresis for noise immunity. Each buffer processes the input signal independently and generates its own output signal, allowing both speed and noise immunity requirements to be met simultaneously through functional segmentation.
Solution Approach 2:
The output block implements a feedback mechanism where the first output signal controls the timing of state transitions while the second output signal controls state locking. This feedback logic ensures that transitions only occur when both buffers agree, reducing erroneous transitions without requiring complex additional circuitry.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables high-speed operation while providing a high degree of noise immunity, reducing errors in signal transitions and maintaining system reliability even under noisy conditions.
Implementation Method 1
The second buffer exhibits hysteresis with a lower threshold and an upper threshold
Implementation Method 2
The first buffer also exhibits hysteresis with a lower threshold and an upper threshold
Data Source
AI summary
This disclosure provides examples of circuits, devices, systems, and methods for providing high speed operation with high noise immunity. In one implementation, a circuit includes a first buffer configured to receive an incoming signal and to generate a first output signal. The circuit also includes a second buffer configured to receive the incoming signal and to generate a second output signal. The second buffer exhibits hysteresis with lower and upper thresholds. The circuit also includes an output block configured to receive the first and second output signals and to generate a third output signal. The output block is configured to switch a logic state of the third output signal in response to a transition of a logic state of the first output signal, and to lock the logic state of the third output signal until the output block receives a transition of a logic state of the second output signal.