Dual Buffer Layer Structure for Passivation Stress Relief

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Solution Overview

Problem

As integrated circuit (IC) package sizes decrease, stress at the interface between buffer layers increases, leading to potential defects such as peeling and cracking in the passivation layer, which affects the reliability and stability of the IC structure.

Innovation Solution

The use of a dual buffer layer system, where a first polymeric layer is partially over the contact pad and a second buffer layer completely covers it, reduces stress mismatch by absorbing and distributing tensile stress, thereby reducing the stress applied to the passivation layer by 40% to 60%.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of moving object

If package size is decreased, then integration density is improved, but stress at the buffer layer interface increases causing peeling and cracking defects

Engineering Contradiction:
Improvepackage sizeVSAvoidpassivation layer integrity
Core Design Contradiction:
Area of moving objectVSReliability

Solution Approach 1:

The buffer layer is divided into two separate layers (first buffer layer and second buffer layer) with different material compositions. The first buffer layer contains a hard mask material while the second buffer layer contains a polymer material, allowing each layer to address different stress characteristics and preventing the peeling and cracking defects that occur in single-layer buffer structures.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The dual buffer layer structure combines two different materials (hard mask material and polymer material) with distinct mechanical properties. This composite approach allows the structure to accommodate stress mismatch between the semiconductor die and package substrate more effectively than a single homogeneous material, thereby preventing interface failure in miniaturized packages.

Inventive Principle:
Principle #40Composite materials

2Stress or pressure

If buffer layer thickness is increased, then stress absorption is improved, but manufacturing complexity increases

Engineering Contradiction:
Improvestress mismatchVSAvoidbuffer layer structure
Core Design Contradiction:
Stress or pressureVSDevice complexity

Solution Approach 1:

Instead of using a single thick buffer layer that would be difficult to manufacture and control, the buffer function is segmented into two thinner layers with different materials. Each layer can be deposited and controlled independently using standard semiconductor fabrication processes, reducing manufacturing complexity while still providing sufficient stress absorption capability.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The solution changes the material composition parameter of the buffer layer rather than simply increasing thickness. By introducing a second layer with different mechanical properties (polymer material), the structure achieves better stress mismatch accommodation without requiring excessive thickness, thereby simplifying the overall device structure and manufacturing process.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enhances the reliability and stability of the IC structure by minimizing the risk of defects and improving physical and electrical isolation, while maintaining structural support during packaging processes.

Implementation Method 1

reduces stress mismatch by absorbing and distributing tensile stress

Methodology Applied
Scientific EffectStress distribution: Elasticity

Data Source

PatentUS11810879B2Semiconductor structure including buffer layer
Publication Date: 2023.11.07 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US11810879B2 patent drawing
  • US11810879B2 patent drawing
  • US11810879B2 patent drawing

AI summary

A semiconductor structure includes a first contact pad over an interconnect structure. The semiconductor structure further includes a second contact pad over the interconnect structure, wherein the second contact pad is electrically separated from the first contact pad. The semiconductor structure further includes a first buffer layer over the first contact pad, wherein the first buffer layer is partially over the second contact pad, and an edge of the second contact pad farthest from the first contact pad extends beyond the first buffer layer.