Dual Buffer Receiver for Plesiochronous Clock Domain Synchronization
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Solution Overview
Problem
In plesiochronous digital circuits, the design of elastic buffers is complex due to the need to manage clock compensation and lane synchronization across multiple lanes, leading to increased complexity and resource consumption in clock domain transitions.
Innovation Solution
A receiver system using two buffers to synchronize incoming data streams, where symbols are written to a first buffer at one rate and read from both buffers at a second rate, with placeholder symbols used to prevent overflow and underflow, and periodic alignment symbols to align multiple symbol streams.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single elastic buffer is used to synchronize plesiochronous streams, then clock domain transition is achieved, but device complexity increases due to the need for overflow/underflow compensation and clock compensation sequence insertion/detection
Solution Approach 1:
The patent divides the single complex elastic buffer into two simpler buffers: a first buffer that receives the plesiochronous input stream and a second buffer that outputs to the synchronous system. This segmentation eliminates the need for the first buffer to handle clock compensation sequences and reduces overflow/underflow complexity, as each buffer has a simplified function.
Solution Approach 2:
The first buffer acts as an intermediary between the plesiochronous input stream and the second buffer. It absorbs the clock frequency differences and produces a steady output stream to the second buffer, thereby shielding the second buffer from the complexity of clock compensation and sequence insertion/detection.
2Reliability
If clock compensation sequences are inserted and detected to prevent overflow and underflow, then data loss is prevented, but the number of processing operations increases
Solution Approach 1:
The patent extracts the clock compensation sequence insertion and detection functions from the buffer management logic. By having the first buffer operate independently with its own simple overflow/underflow handling, the complex sequence processing is removed from the critical data path, reducing processing operations.
Solution Approach 2:
The first buffer serves itself by independently managing its own overflow and underflow conditions through simple control logic that does not require complex sequence insertion or detection. This self-service approach reduces the overall processing burden on the system.
3Reliability
If multiple lanes are synchronized using a complex state machine, then lane alignment is achieved, but resource consumption increases
Solution Approach 1:
The patent segments the lane synchronization function into separate handling for each lane through the first buffer, rather than using a single complex state machine that processes all lanes together. This allows each lane to be synchronized independently with simpler logic, reducing overall resource consumption.
Data Source
AI summary
A receiver for receiving a stream of symbols clocked at a first rate, and providing the symbols at a second clock rate uses two buffers. Incoming symbols are written to a first dual clock buffer at the first rate, and read from the first and second buffer, at the second rate. Underflow of the first buffer is signaled to the second buffer, thereby avoiding the need to insert defined clock compensation symbols at the second rate. Symbols received at the second buffer while underflow is signaled may be ignored. Conveniently, the second buffer may also be used to align symbol data across multiple symbol streams using periodic alignment symbols. An exemplary embodiment conforms to the PCI Express standard.