Dual Input Buffer Switching for SDRAM Self-Refresh Timing
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Solution Overview
Problem
Existing input buffer systems for synchronous dynamic random access memory (SDRAM) suffer from incorrect setup times during self refresh functions due to asymmetrical signal transition times from logic-high to logic-low and vice versa.
Innovation Solution
A dual-input buffer switching system comprising a first input buffer for outputting a signal at logic-high voltage, a second input buffer for outputting a signal at logic-low voltage, and a multiplexer that switches between these signals based on a self-refresh signal to ensure symmetrical transition times.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single input buffer is used to output signals for both logic-high and logic-low voltages, then the device complexity is reduced, but the transition times from logic-high to logic-low and vice versa become asymmetrical, causing incorrect setup times for SDRAM self refresh functions
Solution Approach 1:
The single input buffer is segmented into two separate input buffers: a first input buffer for outputting signals at logic-high voltage and a second input buffer for outputting signals at logic-low voltage. Each buffer is independently optimized to achieve symmetrical transition times, thereby resolving the setup time accuracy issue while maintaining reasonable device complexity through functional division
Solution Approach 2:
Different input buffers are assigned different local qualities (logic-high vs logic-low voltage output characteristics) to optimize their respective transition times. The first input buffer is designed with characteristics optimized for high-to-low transitions, while the second input buffer is optimized for low-to-high transitions, ensuring symmetrical overall performance
2Device complexity
If a single input buffer is used, then the device complexity is reduced, but the reliability of SDRAM self refresh function is compromised due to incorrect setup times
Solution Approach 1:
The buffer system is segmented into specialized first and second input buffers that independently handle logic-high and logic-low voltage transitions respectively. This segmentation ensures that each buffer type is optimized for its specific voltage transition, guaranteeing correct setup times and thereby improving the reliability of SDRAM self refresh functions
Solution Approach 2:
A multiplexer is introduced as an intermediary component to selectively switch between the first input buffer output and the second input buffer output based on the self refresh signal state. This intermediary ensures that the correct buffer output is selected at the appropriate time, maintaining signal integrity and reliability
3Device complexity
If asymmetrical transition times are accepted, then the device complexity is reduced, but the setup time accuracy for self refresh functions becomes incorrect
Solution Approach 1:
The buffer system is divided into two specialized buffers with distinct voltage output characteristics. The first input buffer is optimized for logic-high voltage output with transition times optimized for high-to-low transitions, while the second input buffer is optimized for logic-low voltage output with transition times optimized for low-to-high transitions. This segmentation achieves symmetrical overall transition times without excessive complexity
Solution Approach 2:
The invention changes the voltage level parameter of the buffer outputs - the first input buffer outputs at logic-high voltage while the second input buffer outputs at logic-low voltage. This parameter change allows each buffer to be optimized for its specific voltage level, achieving symmetrical transition times and correct setup time accuracy
Data Source
AI summary
An input buffer system with a dual-input buffer switching function includes a first input buffer, a second input buffer, and a multiplexer. The first input buffer is used for outputting a first signal when an input signal is at a logic-high voltage, and the first input buffer is turned off when the input signal is at a logic-low voltage. The second input buffer is used for outputting a second signal when the input signal is at the logic-low voltage. The multiplexer is coupled to the first input buffer and the second input buffer for outputting the first signal or the second signal according to a self refresh signal.