Dual Bus Data Mapping for Non-Volatile Memory Sensing
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Solution Overview
Problem
The scaling down of memory device dimensions leads to significant parasitic capacitance between bit lines, causing coupling noise and read errors, which worsen sensing accuracy and increase bit line settling time, degrading read performance.
Innovation Solution
Implementing a data mapping method that senses odd-numbered bit lines separately from even-numbered bit lines, using dual data buses for same-tier and cross-tier transfers, and configuring sensing circuitry with separate cache access lines to reduce coupling noise and bit line settling time without degrading performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory device dimensions are scaled down to increase storage density, then storage capacity is improved, but parasitic capacitance between bit lines increases causing coupling noise and read errors
Solution Approach 1:
The patent divides the bit line sensing operation into separate segments by alternating between even-numbered and odd-numbered bit lines. This segmentation isolates the sensing operations, reducing capacitive coupling noise between adjacent bit lines and improving read accuracy in scaled-down memory devices
2Productivity
If conventional sensing methods are used to read all bit lines, then data transfer is simplified, but coupling noise increases and bit line settling time increases degrading read performance
Solution Approach 1:
The patent implements periodic sensing operations that alternate between even and odd bit line sets. This periodic action allows bit lines to settle more quickly between sensing operations, reducing settling time while maintaining efficient data transfer through structured alternation patterns
Data Source
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Figure 3A~3B
Figure 4A
AI summary
Sensing techniques and associated circuitry are provided for use with a memory device. The techniques are suited for sensing operations involving even-numbered or odd-numbered bit lines. In one approach, a mapping between caches and sense amplifiers in a sensing circuit is modified by using dual data buses. One bus is used for same-tier transfers and the other is used for cross-tier transfers. Each tier comprises a set of sense amplifiers and a corresponding set of caches. This approach does not require a modification of the input/output path which is connected to the sensing circuitry.