Dual Bus Master FIFO Data Transfer for Concurrent Read-Write
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Solution Overview
Problem
Traditional Peripheral Direct Memory Access (PDMA) technology is inefficient in processing data transmissions between peripheral devices and system memory, as it requires sequential read and write operations, limiting data transmission speed.
Innovation Solution
A data transmission device with two bus master control circuits and FIFO circuits is employed to enable simultaneous read and write operations between peripheral devices and system memory, utilizing separate control circuits and buffers to manage data transmission efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a single bus master control circuit is used to perform sequential read and write operations, then the device complexity is reduced, but the data transmission speed decreases
Solution Approach 1:
The single bus master control circuit is segmented into two independent bus master control circuits (first and second). Each circuit handles specific operations (read or write) independently, allowing simultaneous execution of multiple operations without interfering with each other, thus increasing data transmission speed while maintaining manageable device complexity through modular design
Solution Approach 2:
The system transitions from sequential single-dimensional operation to parallel multi-dimensional operation by introducing multiple bus master control circuits operating simultaneously. The first bus master control circuit handles read operations while the second handles write operations, creating parallel data transmission paths that increase overall throughput
2Productivity
If sequential read and write operations are performed, then the device complexity is reduced, but the data transmission efficiency decreases
Solution Approach 1:
The system implements continuous useful action by eliminating idle time between read and write operations. While the first bus master control circuit performs read operations, the second simultaneously performs write operations, ensuring that data transmission resources are continuously utilized without interruption, thereby maximizing productivity
Solution Approach 2:
The system prepares data in advance by performing read operations in parallel with write operations. Data is pre-fetched and buffered while simultaneously being written to destination, reducing waiting time and improving overall data transmission efficiency through overlapping operations
3Adaptability or versatility
If a single buffer is used for data buffering, then the device complexity is reduced, but the ability to handle concurrent operations decreases
Solution Approach 1:
The single buffer is segmented into multiple independent buffers (first buffer, second buffer, third buffer, fourth buffer), each dedicated to specific data transmission paths. This segmentation allows concurrent read and write operations to access different buffers simultaneously without data conflicts, enhancing adaptability while maintaining organized structure
Solution Approach 2:
Multiple buffers act as intermediaries between different bus master control circuits and memory systems. Each buffer serves as a temporary storage intermediary that decouples the timing and speed differences between read and write operations, enabling smooth data flow and concurrent operations
Data Source
AI summary
An embodiment of the invention provides a data transmission device. The data transmission device includes a first bus master control circuit, a second bus master control circuit, a storage circuit, a first control circuit and a second control circuit. The first bus master control circuit processes data transmissions associated with a peripheral device. The second bus master control circuit processes data transmissions associated with a system memory. The storage circuit stores information and instructions for data transmission. The first control circuit controls the first bus master control circuit according to the information and the instructions. The second control circuit controls the second bus master control circuit according to the information and the instructions.