Dual Bus Memory Array for High-Voltage Scaling
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Solution Overview
Problem
In three-dimensional memory technology, the high voltages required for programming and erasing passive element memory cells pose challenges for scaling down word line and bit line pitches, as high-voltage transistors do not scale well, leading to compatibility issues with smaller array line pitches and increased leakage current in unselected memory cells.
Innovation Solution
The implementation of a memory array with dual data busses and hierarchical decoding arrangements allows for simultaneous selection and coupling of word lines and bit lines across multiple array blocks, reducing voltage requirements for decoder circuits and minimizing leakage current by biasing unselected memory cells appropriately.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If high-voltage transistors are used for programming and erasing memory cells, then programming and erasing operations can be performed, but the transistors do not scale well with decreasing word line and bit line pitches
Solution Approach 1:
The memory array is divided into multiple blocks, each block independently selectable via block select lines. This segmentation allows different blocks to be activated independently, enabling scalable architecture where high-voltage transistor requirements are localized to specific blocks rather than requiring all transistors to support high voltage.
Solution Approach 2:
High-voltage transistor requirements are localized to specific memory blocks that need programming or erasing operations. Block select lines enable only the necessary blocks to be activated, meaning high-voltage transistors are only required in actively operated blocks rather than throughout the entire array, improving scalability.
2Reliability
If high-voltage transistors are used to provide sufficient voltage across selected memory cells, then programming and erasing can be achieved, but leakage current increases in unselected memory cells
Solution Approach 1:
The memory array is segmented into multiple blocks with independent block select lines. This allows precise control where only selected blocks receive high-voltage signals for programming or erasing, while unselected blocks remain in a low-voltage state, minimizing leakage current in non-active regions.
Solution Approach 2:
Block select lines act as intermediary control signals that gate the activation of memory blocks. These select lines enable or disable entire blocks before high-voltage operations occur, serving as a mediator that prevents high-voltage signals from reaching unselected blocks and causing leakage current.
3Device complexity
If the memory array uses larger block sizes to reduce the number of blocks, then decoder complexity decreases, but the voltage requirements for high-voltage transistors increase
Solution Approach 1:
The memory array is divided into multiple manageable blocks, each with its own block select line. This segmentation creates a hierarchical decoder structure where the overall addressing is split into block-level and cell-level decoding, reducing the complexity of individual decoders while distributing voltage stress across multiple smaller blocks rather than requiring one large block with excessively high voltage requirements.
Solution Approach 2:
The memory addressing is organized in a hierarchical structure with block select lines providing an additional dimension of control. This multi-level addressing scheme (block level + cell level) reduces decoder complexity by breaking down the single large decoding task into smaller, manageable stages, while also distributing voltage requirements across multiple blocks.
Data Source
AI summary
Circuits and methods are described for decoding exemplary memory arrays of programmable and, in some embodiments, re-writable passive element memory cells, which are particularly useful for extremely dense three-dimensional memory arrays having more than one memory plane. In addition, circuits and methods are described for selecting one or more array blocks of such a memory array, for selecting one or more word lines and bit lines within selected array blocks, for conveying data information to and from selected memory cells within selected array blocks, and for conveying unselected bias conditions to unselected array blocks.