Dual-Bus Memory Component for In-Memory Machine Learning
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Solution Overview
Problem
Conventional memory sub-systems experience latency issues during machine learning operations due to the need for external buses and interfaces to transmit data, models, and intermediate results between memory components and machine learning processors, which hinders performance and efficiency.
Innovation Solution
Integrating internal logic within memory components to perform machine learning operations, eliminating the need for external processors and buses by using digital logic or resistor arrays to implement machine learning models directly within the memory cells or sub-system controllers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If data is transmitted between memory components and machine learning processors using external buses, then the memory sub-system can perform both storage and machine learning operations, but latency increases and performance deteriorates
Solution Approach 1:
The patent combines machine learning processing logic directly within the memory component, merging storage and processing functions into a single integrated unit. This eliminates the need for external buses and separate processors, thereby reducing latency while maintaining dual functionality of storage and machine learning operations
Solution Approach 2:
The memory component is designed to perform multiple functions: traditional data storage and machine learning operations. By integrating processing capabilities within the memory component itself, the system achieves multi-functionality without requiring separate processing units and data transmission pathways
2Productivity
If separate buses are used for memory data and machine learning data, then data transmission can occur simultaneously, but device complexity increases
Solution Approach 1:
The patent merges memory operations and machine learning operations into a single integrated component with unified access logic. This consolidation eliminates the need for separate buses while maintaining the ability to handle different types of operations simultaneously through intelligent resource management within the unified architecture
3Reliability
If external processors are used for machine learning operations, then specialized processing can be performed, but the need for additional interfaces and buses increases
Solution Approach 1:
The patent integrates machine learning processing logic directly within the memory component, merging storage and processing functions into a single unit. This eliminates external processors and their associated interfaces, reducing device complexity while maintaining specialized processing capabilities through dedicated logic circuits within the memory component
Data Source
AI summary
Memory cells can include a memory region to store a machine learning model and input data and another memory region to store host data from a host system. An in-memory logic can be coupled to the plurality of memory cells and can perform a machine learning operation by applying the machine learning model to the input data to generate an output data. A bus can receive additional host data from the host system and can provide the additional host data to the memory component for the other memory region of the plurality of memory cells. An additional bus can receive machine learning data from the host system and can provide the machine learning data to the memory component for the in-memory logic that is to perform the machine learning operation.