Dual Cache L2P Buffer for Managed NAND Read Latency
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Solution Overview
Problem
Managed NAND (mNAND) devices face latency issues due to the time required to read logical-to-physical (L2P) table entries during read operations, and Host Performance Booster (HPB) operations incur additional latency from sending L2P tables to the host system, necessitating a solution to manage the mNAND L2P buffer and HPB operations effectively.
Innovation Solution
The system divides the L2P buffer into a first cache for storing blocks of the L2P table and a second cache for tracking activated regions for HPB operations, with the first cache updated after each read and the second cache using a bit map to indicate active regions, allowing direct loading of L2P tables from the first cache and reducing latency by skipping address translation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If L2P table entries are read during read operations, then address translation is completed, but latency increases due to the time required to read the entries
Solution Approach 1:
The system pre-loads L2P table entries into a cache buffer before they are actually needed for read operations. When a read operation is initiated, the corresponding L2P entries are already available in the cache, eliminating the latency associated with reading them from the L2P table at the moment of access. This preliminary action of caching resolves the contradiction by making address translation faster without compromising read speed.
2Productivity
If L2P tables are sent to the host system for HPB operations, then address translation can be skipped, but additional latency is incurred from sending the tables
Solution Approach 1:
The system extracts only the necessary L2P table entries related to activated regions and stores them in a dedicated cache buffer, rather than sending the entire L2P table to the host system. This selective extraction allows HPB operations to skip address translation for activated regions while minimizing the time and overhead associated with preparing and transmitting L2P data, thus resolving the contradiction between HPB operation speed and latency.
3Adaptability or versatility
If the L2P buffer stores complete L2P tables, then all address translations can be performed, but storage requirements increase
Solution Approach 1:
The system implements a cache buffer that stores only the L2P table entries corresponding to activated regions, rather than maintaining complete L2P tables for all regions. This localized storage approach provides adequate address translation capability for the currently active regions while significantly reducing the overall storage space required in the L2P buffer, thus resolving the contradiction between adaptability and storage requirements.
Data Source
AI summary
Methods, systems, and devices for read operations for regions of a memory device are described. In some examples, a memory device may include a first cache for storing mappings between logical addresses and physical addresses of the memory device, and a second cache for storing indices associated with entries removed from the first cache. The memory device may include a controller configured to load mappings to the first cache upon receiving read commands. When the first cache is full, and when the memory device receives a read command, the controller may remove an entry from the first cache and may store an index associated with the removed entry to the second cache. The controller may then transmit a mapping associated with the index to a host device for use in a HPB operation.