Dual-Cache L2P Translation for SSD Performance
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Solution Overview
Problem
In solid-state drives (SSDs) using NAND type flash memory, the performance of logical-to-physical address translation is degraded due to high cache miss rates in the logical-to-physical address translation table cache, leading to increased latency and costs associated with using sufficient DRAM capacity for efficient address translation.
Innovation Solution
Implementing a dual-cache system in the random access memory, comprising an L2P table cache for storing uncompressed address translation data and a compressed L2P table cache for storing compressed data, allowing for efficient use of DRAM capacity and reducing cache miss rates by utilizing the compressed cache when misses occur in the primary cache.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single L2P table cache is used for address translation, then the cache structure is simple, but the cache miss rate is high leading to degraded performance
Solution Approach 1:
The patent divides the single L2P table cache into two separate caches: a first L2P table cache and a second L2P table cache. This segmentation allows each cache to be optimized for different purposes, with the first cache handling standard address translations and the second cache handling compressed address translations, thereby reducing overall cache miss rates and improving address translation performance without excessive complexity
Solution Approach 2:
The patent introduces a new dimension to the cache system by adding compression capability. The second L2P table cache stores compressed address translation data, creating an additional layer of caching strategy. This dimensional change from single-format caching to multi-format caching (compressed and uncompressed) enables the system to handle address translations more efficiently by selecting the appropriate cache based on data patterns
2Productivity
If DRAM capacity is increased to reduce cache miss rates, then address translation efficiency improves, but system cost increases
Solution Approach 1:
The patent changes the parameter of data representation by implementing compression in the second L2P table cache. By storing compressed address translation data, the system achieves the same caching capacity with reduced DRAM requirements. This parameter change from uncompressed to compressed storage allows the system to maintain high address translation efficiency while using less DRAM capacity, thereby reducing system cost
3Productivity
If a dual-cache system with compression is implemented, then DRAM capacity is optimized and cache miss rates are reduced, but the device complexity increases
Solution Approach 1:
The patent introduces a compression management mechanism that acts as an intermediary between the two L2P table caches. This intermediary manages the compression and decompression of address translation data, coordinating between the first cache (uncompressed) and second cache (compressed). While this adds some complexity, it enables efficient DRAM usage and reduced cache miss rates by automatically selecting the appropriate cache format based on access patterns
Data Source
AI summary
According to one embodiment, a memory system executes, when first address translation data including a first physical address indicating a physical storage location of the nonvolatile memory where data corresponding to a first logical address specified by a host is stored does not exist in a first cache and first compressed address translation data corresponding to the first address translation data exists in a second cache, an operation for storing uncompressed address translation data obtained by decompressing the first compressed address translation data in the second cache in the first cache and an operation for acquiring the first physical address from the uncompressed address translation data.