Dual-Cache Memory System for Lookup Table Compression
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Solution Overview
Problem
In memory systems with large user capacities, the increasing size of the lookup table (LUT) required for address translation leads to higher costs due to the need for larger cache memories, and existing compression methods do not guarantee high compression rates, often resulting in increased access times and reduced performance.
Innovation Solution
The implementation of a dual-cache system with a non-compression LUT cache and a compression LUT cache, where the memory controller dynamically adjusts the capacity ratio based on the frequency of sequential writes and cache hit rates to optimize storage efficiency and access speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the cache memory capacity is increased to store larger lookup tables for address translation, then the address translation speed is improved, but the system cost increases
Solution Approach 1:
The patent divides the cache memory into two separate caches: a first cache for storing uncompressed lookup table segments and a second cache for storing compressed lookup table segments. This segmentation allows the system to optimize storage efficiency by compressing only the portions of the lookup table that are not frequently accessed, while maintaining fast access to frequently used segments in the uncompressed cache.
Solution Approach 2:
The patent changes the compression state parameter of different lookup table segments based on their access patterns. Frequently accessed segments are kept in an uncompressed state in the first cache for fast access, while less frequently accessed segments are stored in a compressed state in the second cache to reduce overall memory capacity requirements.
2Quantity of substance
If compression is applied to lookup table segments, then the cache memory capacity is reduced, but the access time increases due to compression/decompression overhead
Solution Approach 1:
The patent segments the lookup table into multiple segments and applies compression selectively to certain segments based on their access frequency. This allows the system to maintain uncompressed segments for fast access while using compression for less frequently accessed segments, thereby reducing overall capacity without significantly impacting access time for critical data.
Solution Approach 2:
The patent dynamically manages the compression state of lookup table segments by monitoring access patterns. When a compressed segment is accessed, it is decompressed and may be transferred to or replicated in the uncompressed cache. This dynamic adjustment ensures that frequently accessed data is available in uncompressed form while maintaining compression benefits for less frequently accessed data.
3Device complexity
If a single cache is used for all lookup table segments, then the device complexity is low, but the cache hit rate decreases due to inefficient utilization of cache capacity
Solution Approach 1:
The patent introduces a segmented cache structure with two distinct caches: one for uncompressed segments and one for compressed segments. This segmentation improves cache hit rates by ensuring that frequently accessed segments are stored in the uncompressed cache where they can be quickly retrieved, while the compressed cache stores less frequently accessed segments, thereby optimizing overall cache utilization.
Solution Approach 2:
The patent applies different storage qualities (compressed vs. uncompressed) to different segments of the lookup table based on their specific access patterns and importance. Critical segments that require fast access are stored in uncompressed form in the first cache, while less critical segments are stored in compressed form in the second cache, optimizing both performance and capacity utilization.
Data Source
AI summary
A memory system is connectable to the host. The memory system includes a nonvolatile first memory, a second memory in which a plurality of pieces of first information each correlating a logical address indicating a location in a logical address space of the memory system with a physical address indicating a location in the first memory are stored, a volatile third memory including a first cache and a second cache, a compressor configured to perform compression on the plurality of pieces of first information, and a memory controller. The memory controller stores the first information not compressed by the compressor in the first cache, stores the first information compressed by the compressor in the second cache, and controls a ratio between a first capacity, which is a capacity of the first cache, and a second capacity, which is a capacity of the second cache.