Dual Cache Memory System Address History Pre-fetching
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Solution Overview
Problem
In SSDs and other storage systems using NAND type flash memory, the large buffer size required for pre-fetching data to enhance access performance leads to internal bandwidth compression and complex buffer management, which can suppress performance due to short processing times with high-speed hosts.
Innovation Solution
A memory system with a non-volatile memory cell array, cache regions, and a controller that manages address information histories to efficiently transfer data between cache regions and the memory cell array, allowing for pre-fetching of data without reading it from the array if the address matches cache histories, thereby reducing latency and improving performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If pre-fetching of data is carried out from NAND type flash memory to enhance access performance, then access performance is improved, but buffer size becomes large leading to internal bandwidth compression and complex buffer management
Solution Approach 1:
The buffer memory is divided into multiple cache regions (first cache region and second cache region) to segment the buffer management task. Each cache region independently stores data with its own address history, simplifying the overall buffer management complexity while maintaining pre-fetching capabilities for enhanced access performance.
Solution Approach 2:
The system performs preliminary action by pre-fetching data from NAND type flash memory into cache regions before actual access requests arrive. The address history function predicts and prepares data in advance, improving access performance without requiring excessive buffer size for all possible data.
2Loss of time
If pre-fetching of data is carried out to hide waiting time, then waiting time is reduced, but buffer size becomes large causing internal bandwidth compression
Solution Approach 1:
The system applies partial action by pre-fetching only the necessary amount of data into limited cache regions based on address history prediction, rather than buffering all possible data. This reduces the buffer size requirement while still effectively hiding waiting time for predicted access patterns.
Solution Approach 2:
Cache regions serve as intermediaries between the NAND type flash memory and the host. They hold frequently accessed or predicted data, reducing the need for large buffer sizes while effectively hiding waiting time by providing data from the intermediate cache rather than from slow flash memory.
3Speed
If data is transferred from cache regions to buffer memory without reading from memory cell array when address matches history, then readout speed is improved, but requires sophisticated address matching logic
Solution Approach 1:
The address history is segmented into multiple independent cache regions with separate history tables. This segmentation simplifies the address matching logic by limiting the search scope to specific regions rather than requiring system-wide address matching, while still achieving fast readout speeds through regional cache hits.
Solution Approach 2:
The system maintains copies of address information in history tables for each cache region. When a read request arrives, the system checks these copied address histories to determine if data can be served from cache without accessing the memory cell array, improving readout speed with simplified copying-based address matching.
Data Source
AI summary
According to one embodiment, a memory system includes a chip including a cell array and first and second caches configured to hold data read out from the cell array; an interface configured to manage a first and a second addresses; a controller configured to issue a readout request to the interface; and a buffer configured to hold the data from the chip. The interface transfers the data in the first cache to the buffer without reading out the data from the cell array if the readout address matches the first address, transfers the data in the second cache to the buffer without reading out the data from the cell array if the readout address matches the second address, and reads out the data from the cell array and transfers the data to the buffer if the readout address does not match either one of the first or second address.