Dual Cache Data Segment Promotion and Pinning

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Solution Overview

Problem

In computing systems with multi-level caches, managing partial data segments in secondary caches, such as Flash Cache, leads to wasted memory space and increased input/output activity, as these systems often incur resource consumption and performance slowdowns when filling 'holes' in partial tracks.

Innovation Solution

The solution involves promoting whole data segments to both lower and higher levels of cache, where requested data is positioned in the Most Recently Used (MRU) portion of the higher level cache and unrequested data is pinned in the Least Recently Used (LRU) portion until the write to the lower level cache is complete, ensuring efficient management and elimination of partial data segments.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If partial data segments are written to secondary cache, then cache storage capacity is utilized, but wasted memory space occurs and additional I/O activity is incurred

Engineering Contradiction:
Improvecache storage utilizationVSAvoidI/O activity and resource consumption
Core Design Contradiction:
Quantity of substanceVSLoss of energy

Solution Approach 1:

The patent segments data into whole data segments that are promoted to both lower and higher levels of cache simultaneously. By processing complete segments rather than partial tracks, the system avoids the fragmentation problem while maintaining efficient cache utilization across multiple cache levels.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent performs preliminary actions by promoting entire data segments to both cache levels before any write operations complete. This preliminary promotion ensures that cache space is efficiently utilized from the outset, preventing the need for subsequent I/O operations to fill partial tracks.

Inventive Principle:
Principle #10Preliminary action

2Area of stationary object

If partial tracks are used in secondary cache, then some storage space is occupied, but returning to disk drives to fill holes incurs additional I/O activity

Engineering Contradiction:
Improvestorage space occupationVSAvoidsystem performance
Core Design Contradiction:
Area of stationary objectVSProductivity

Solution Approach 1:

The patent merges the promotion of whole data segments to both lower and higher cache levels into a single coordinated operation. This merging eliminates the need for separate I/O operations to fill partial tracks, as the entire segment is properly positioned in cache space in one action.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent ensures continuity of useful action by maintaining pinned unrequested data in place until the write to lower level cache completes. This continuous management prevents interruptions and additional I/O operations, keeping the cache system operating efficiently without performance degradation.

Inventive Principle:
Principle #20Continuity of useful action

3Loss of substance

If whole data segments are promoted to both lower and higher cache levels, then storage space waste is minimized, but data management complexity increases

Engineering Contradiction:
Improvewasted storage spaceVSAvoiddata management complexity
Core Design Contradiction:
Loss of substanceVSDevice complexity

Solution Approach 1:

The patent introduces pinned data as an intermediary state between promotion and write completion. This intermediary mechanism simplifies data management by automatically holding unrequested data in place without requiring complex coordination, thereby reducing management complexity while eliminating storage waste.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS8688913B2Management of partial data segments in dual cache systems
Publication Date: 2014.04.01 INTERNATIONAL BUSINESS MACHINE CORPORATION
  • US8688913B2 patent drawing
  • US8688913B2 patent drawing
  • US8688913B2 patent drawing

AI summary

For movement of partial data segments within a computing storage environment having lower and higher levels of cache by a processor, a whole data segment containing one of the partial data segments is promoted to both the lower and higher levels of cache. Requested data of the whole data segment is split and positioned at a Most Recently Used (MRU) portion of a demotion queue of the higher level of cache. Unrequested data of the whole data segment is split and positioned at a Least Recently Used (LRU) portion of the demotion queue of the higher level of cache. The unrequested data is pinned in place until a write of the whole data segment to the lower level of cache completes.