Dual-Capacitor Bootstrap Circuit for Low Voltage Power Converters
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Solution Overview
Problem
Existing power converters face challenges in operating efficiently at low input voltages due to the large size and high power losses associated with p-type FETs, and the need for large bootstrap capacitors in n-type FETs to achieve conductive states, which increases physical size and cost.
Innovation Solution
A dual-capacitor bootstrap circuit acts as a tripling charge pump, using two capacitors in series to achieve higher gate-to-source voltages with reduced overall capacitance, thereby minimizing physical size and cost while maintaining performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If a single large bootstrap capacitor is used to achieve sufficient gate-to-source voltage, then the voltage requirement is met, but the physical size and cost increase
Solution Approach 1:
The single large bootstrap capacitor is divided into multiple smaller capacitors (first bootstrap capacitor, second bootstrap capacitor, third bootstrap capacitor) connected in series. This segmentation allows achieving the required gate-to-source voltage through voltage division while reducing the surface area of each individual capacitor, thereby resolving the contradiction between voltage requirement and physical size.
Solution Approach 2:
The solution transitions from a single-capacitor architecture to a multi-capacitor series arrangement, adding the dimension of voltage distribution across multiple elements. This dimensional change in the circuit topology enables the same voltage output with reduced individual component sizes, effectively addressing the area-constraint problem.
2Adaptability or versatility
If p-type FETs are used to operate at low input voltages, then the voltage compatibility is improved, but the device size and power losses increase
Solution Approach 1:
The invention changes the electrical parameters of the gate drive circuit by using multiple bootstrap capacitors in series to generate higher gate-to-source voltages. This parameter change enables n-type FETs to operate effectively at low input voltages without requiring large device sizes or suffering from high power losses, thus resolving the contradiction between voltage adaptability and energy efficiency.
3Strength
If a single large bootstrap capacitor is used, then the voltage requirement is met, but the recharging time increases
Solution Approach 1:
Dividing the large capacitor into multiple smaller series capacitors reduces the recharging time for each individual capacitor. Since they are connected in series, the overall recharging process is accelerated as each smaller capacitor charges faster, resolving the contradiction between maintaining sufficient voltage and reducing recharging time.
Solution Approach 2:
The multi-capacitor configuration enables periodic charging cycles where each capacitor can be charged and discharged in sequence. This periodic action allows for faster overall recharging compared to a single large capacitor, as the charging current can be distributed across multiple smaller elements, reducing the total time loss.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The dual-capacitor bootstrap circuit reduces the required capacitance and surface area, enhancing power efficiency and extending the operational time of power converters at low voltages by recovering charge and reducing recharging time.
Implementation Method 1
The first capacitor is coupled between the first node and the third node. The second capacitor is coupled between the fourth node and the sixth node.
Implementation Method 2
A dual-capacitor bootstrap circuit acts as a tripling charge pump, using two capacitors in series to achieve higher gate-to-source voltages with reduced overall capacitance
Data Source
AI summary
Aspects of the disclosure provide for a circuit. In some examples, the circuit includes a first transistor, a second transistor, a third transistor, a first capacitor, and a second capacitor. The first transistor comprises a drain terminal coupled to an input voltage node, a source terminal coupled to a first node, and a gate terminal coupled to a second node. The second transistor comprises a drain terminal coupled to a third node, a source terminal coupled to a fourth node, and a gate terminal coupled to a fifth node. The third transistor comprises a drain terminal coupled to a sixth node, a source terminal configured to couple to a gate terminal of a switching transistor, and a gate terminal coupled to a seventh node. The first capacitor is coupled between the first node and the third node. The second capacitor is coupled between the fourth node and the sixth node.