Dual-Capacitor Buffer Circuit for Extended Hold-Up Time

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Solution Overview

Problem

Existing electronic circuits face challenges in extending hold-up time without increasing capacitor size, as the required capacitance is directly proportional to hold-up time and power consumption, leading to larger capacitors for maintaining minimum voltage levels during power outages.

Innovation Solution

A method involving a buffer circuit with two capacitors operating in parallel and series modes, where one capacitor supplies power and regulates voltage by transferring charge to the other during power outages, allowing for reduced overall capacitance while maintaining voltage levels.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Duration of action of moving object

If the capacitance of the capacitor is increased to extend hold-up time, then the hold-up time is improved, but the size of the capacitor increases

Engineering Contradiction:
Improvehold-up timeVSAvoidcapacitor size
Core Design Contradiction:
Duration of action of moving objectVSVolume of moving object

Solution Approach 1:

The capacitor is divided into two separate capacitors (first capacitor and second capacitor) that can operate independently or in parallel. During normal operation, both capacitors are in parallel providing full capacitance. During hold-up mode, only the second capacitor supplies power while the first capacitor regulates voltage by transferring charge, effectively segmenting the functional roles to reduce total capacitance requirement.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The invention changes the operational parameters of the capacitor system by introducing two distinct operating modes (normal mode and hold-up mode) with different capacitance configurations. In hold-up mode, the system transitions from requiring full capacitance for power supply to using a smaller second capacitor for power supply with the first capacitor providing voltage regulation through charge transfer, thereby reducing the capacitance parameter during critical operation.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If the capacitance of the capacitor is increased to maintain minimum voltage level during power outages, then the voltage stability is improved, but the size of the capacitor increases

Engineering Contradiction:
Improvevoltage stabilityVSAvoidcapacitor size
Core Design Contradiction:
ReliabilityVSVolume of moving object

Solution Approach 1:

The voltage regulation function is segmented from the power supply function by assigning different roles to the two capacitors. The second capacitor is dedicated to power supply during hold-up mode, while the first capacitor is dedicated to voltage regulation through charge transfer. This segmentation allows each capacitor to be optimized for its specific function, reducing the total capacitance needed compared to a single capacitor performing both functions.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The first capacitor acts as an intermediary element that transfers charge to the second capacitor to regulate voltage during hold-up mode. This charge transfer mechanism serves as a mediator between the power source and the load, maintaining voltage stability without requiring the second capacitor to be oversized for both power supply and voltage regulation.

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach reduces the overall capacitance needed, enabling smaller capacitors while maintaining hold-up time and voltage stability, thus optimizing capacitor size and energy storage efficiency.

Implementation Method 1

regulating the first voltage includes transferring charge from the first capacitor to the second capacitor

Methodology Applied
Scientific EffectCharge transfer: Capacitance

Data Source

PatentUS12143003B2Method for extending the hold-up time
Publication Date: 2024.11.12 INFINEON TECH AUSTRIA AG
  • US12143003B2 patent drawing
  • US12143003B2 patent drawing
  • US12143003B2 patent drawing

AI summary

Disclosed is a method and a control circuit. The method includes operating a buffer circuit (1) in a first operating mode or a second operating mode. Operating the buffer circuit (1) in the first operating mode includes buffering, by a capacitor parallel circuit including a first capacitor (11) and a second capacitor (12), power (Po) provided by a power source (3) and received by a load (4). Operating the buffer circuit (1) in the second operating mode includes supplying power to the load (4) by the second capacitor (12), and regulating a first voltage (Upn) across the second capacitor (12), wherein regulating the first voltage (Upn) comprises transferring charge from the first capacitor (11) to the second capacitor (12).