Dual-Capping Gate Structure for Backside-Wired Semiconductor Reliability
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Solution Overview
Problem
The increasing demand for compact and high-integration semiconductor memory devices poses challenges in ensuring the reliability of semiconductor memory devices due to reduced design rules and increased routing congestion, making it difficult to secure reliable power delivery and signal routing.
Innovation Solution
The semiconductor device incorporates a front-side and back-side wiring structure with a capping film configuration on gate electrodes, including a first and second capping film, and a gate spacer, which allows for precise alignment of contacts with the source/drain region, enhancing routing resources and reliability by separating gate structures and providing independent power and signal lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If design rules are reduced to increase integration density, then high integration density is achieved, but reliability deteriorates
Solution Approach 1:
The patent transitions from planar 2D wiring to 3D vertical wiring structures, utilizing the depth dimension beneath the semiconductor substrate. Back-side wiring structures are formed below the substrate, allowing power and signal lines to be routed in three dimensions, thereby increasing integration density without compromising reliability through reduced routing congestion and improved design rule adherence.
Solution Approach 2:
The wiring structure is segmented into front-side wiring structures above the substrate and back-side wiring structures below the substrate. This segmentation separates power delivery and signal routing functions across different spatial zones, reducing routing congestion and enhancing both integration density and reliability independently.
2Area of stationary object
If routing congestion increases due to high integration density, then compact design is achieved, but power delivery reliability deteriorates
Solution Approach 1:
Power delivery is extended into the vertical dimension by forming back-side wiring structures below the substrate. This three-dimensional power delivery network reduces lateral routing congestion on the front side while ensuring reliable power distribution to high-density integrated circuits through dedicated vertical interconnects.
3Area of stationary object
If design rules are reduced for compactness, then device compactness is achieved, but manufacturing precision requirements worsen
Solution Approach 1:
The manufacturing process is segmented into separate front-side and back-side processing sequences. This allows independent optimization of each side's manufacturing precision requirements, with alignment marks and reference structures formed on both sides to facilitate precise registration during substrate bonding, thereby reducing overall device area while maintaining manufacturability.
Data Source
AI summary
A semiconductor device includes a front-side wiring structure connected to a signal line, a back-side wiring structure arranged below the front-side wiring structure and connected to a power line, and an electronic element between the front-side wiring structure and the back-side wiring structure, wherein the electronic element includes a plurality of gate structures, each of the plurality of gate structures includes a gate electrode, a capping film, and a gate spacer, and the capping film includes a first capping film and a second capping film, the first capping film being on a bottom surface of the gate electrode, and the second capping film being on a top surface of the gate electrode.