Dual Capping Layer for Dielectric Breakdown Reliability
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Solution Overview
Problem
Modern integrated chip fabrication faces reliability issues due to high porosity in low-k dielectric layers, leading to diffusion of atoms from capping layers into the underlying dielectric material, causing time-dependent dielectric breakdown (TDDB) and voltage breakdown (VBD) in back-end-of-the-line (BEOL) structures.
Innovation Solution
A method involving the deposition of an extreme low-k (ELK) dielectric layer with a high-density first capping layer between metal layer structures, followed by a second capping layer, which has high selectivity to minimize interaction and diffusion, thereby improving dielectric breakdown reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional uniform capping layer is deposited over the low-k dielectric layer and metal layer structures, then the capping layer provides coverage, but atoms diffuse from the capping layer into the porous low-k dielectric layer causing reliability issues
Solution Approach 1:
The single uniform capping layer is segmented into two distinct layers: a first capping layer deposited conformally over the entire surface, and a second capping layer selectively deposited only over metal layer structures. This segmentation allows each layer to perform its specific function - the first layer provides general coverage while the second layer provides targeted protection with high selectivity, preventing atom diffusion into the porous dielectric.
Solution Approach 2:
The patent applies different properties to different parts of the capping structure. The second capping layer is designed with high selectivity to deposit exclusively on metal surfaces, creating a localized protective barrier where it is most needed. This local quality approach ensures that the capping material is present where diffusion occurs (at metal-dielectric interfaces) while avoiding unnecessary material deposition over the dielectric itself.
2Object-generated harmful factors
If the second capping layer is deposited with high selectivity to minimize interaction with the dielectric, then diffusion is reduced, but the deposition process complexity increases
Solution Approach 1:
The first capping layer acts as an intermediary between the dielectric layer and the second capping layer. It provides a conformal base layer that facilitates the selective deposition of the second capping layer. The intermediary first layer enables the second layer to achieve high selectivity through surface property differences, while the two-layer structure itself manages the complexity by dividing the capping function into manageable steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The approach effectively reduces TDDB and VBD by creating a planar surface with metal structures interspersed between capping layers, enhancing the reliability of BEOL structures through controlled diffusion and increased selectivity of the capping layers.
Implementation Method 1
A first capping layer is deposited over the ELK dielectric layer
Implementation Method 2
A second capping layer is deposited over the metal layer structures
Implementation Method 3
The first capping layer has a high selectivity that limits interaction between the second capping layer and the ELK dielectric layer, reducing diffusion of the atoms from the second capping layer to the ELK dielectric layer
Data Source
AI summary
The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method may be performed by forming a first capping layer on a dielectric structure over a substrate, and patterning the dielectric structure and the first capping layer to define cavities within the dielectric structure. A conductive material is formed within the cavities and a second capping layer is formed on the conductive material. An etch stop layer is formed along sidewalls and over an upper surface of the second capping layer. The etch stop layer has a first thickness over the first capping layer and a second thickness over the second capping layer. The first thickness is greater than the second thickness.


