Dual-Carry Gate Driving Circuit for Switch Degradation Relief

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Solution Overview

Problem

Display devices experience reduced lifespan due to degradation of switches in driving circuits, particularly those with high use frequency, leading to inefficiencies in sub-pixel control.

Innovation Solution

A gate driving circuit with a dual carry circuit and clock input circuit that includes pull-up and pull-down transistors, controlled by Q-node and QB-node voltage levels, to manage forward and backward carry signals and clock signals, reducing degradation through optimized signal management.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If switches in driving circuits are used continuously to control sub-pixels, then the display device can maintain its functionality, but the switches degrade over time reducing the device lifespan

Engineering Contradiction:
Improveswitch lifespanVSAvoiddevice operating time
Core Design Contradiction:
ReliabilityVSDuration of action of stationary object

Solution Approach 1:

The patent implements bidirectional driving capability that dynamically switches between forward driving mode and backward driving mode. The driving direction can be changed based on operational requirements, allowing the circuit to adapt its operation pattern. This dynamic switching between different operational states reduces continuous stress on individual switches, thereby extending their lifespan while maintaining continuous device functionality.

Inventive Principle:
Principle #15Dynamics

2Speed

If high use frequency switches are used to improve response speed, then control efficiency increases, but degradation occurs more early

Engineering Contradiction:
Improveswitch response speedVSAvoidswitch durability
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The patent employs periodic alternation between forward driving and backward driving modes. By switching the driving direction periodically or based on operational conditions, the high-frequency switches are given periodic rest periods during mode transitions. This periodic action pattern allows switches to recover from high-stress states, maintaining fast response capability while preventing premature degradation through controlled operational cycles.

Inventive Principle:
Principle #19Periodic action

3Device complexity

If a single driving mode is used to simplify circuit design, then device complexity is reduced, but switch degradation accelerates due to continuous operation

Engineering Contradiction:
Improvecircuit configurationVSAvoidswitch lifespan
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The patent designs the gate driving circuit with multi-functionality, incorporating both forward driving and backward driving capabilities within a single unified circuit structure. The same circuit components can operate in multiple modes (forward mode, backward mode, and intermediate states), eliminating the need for separate dedicated circuits for each mode. This universal design maintains relatively simple overall structure while enabling mode switching to reduce switch degradation.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS12499819B2Gate driving circuit and display device including the same
Publication Date: 2025.12.16 LG DISPLAY CO LTD
  • US12499819B2 patent drawing
  • US12499819B2 patent drawing
  • US12499819B2 patent drawing

AI summary

A display device can include a display panel with a plurality of sub-pixels disposed therein, and a gate driving circuit configured to output a gate signal to the plurality of sub-pixels. The gate driving circuit includes a pull-up transistor controlled by a voltage level of a Q-node, a pull-down transistor configured by a voltage level of a QB-node, a dual carry circuit configured to output a forward carry signal in accordance with the voltage levels of the Q-node and the QB-node in forward driving and output a backward carry signal in accordance with the voltage levels of the Q-node and the QB-node in backward driving, and a clock input circuit configured to apply a forward clock signal to the Q-node when a forward start signal is input and apply a backward clock signal to the Q-node when a backward start signal is input.