Dual-Cell Gray-Code Encoding for Memory Bit Error Reduction

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Solution Overview

Problem

Non-volatile data storage devices face increased bit error rates when storing multiple bits per cell, as the number of data states required to represent additional bits makes it difficult to distinguish between states, leading to errors due to data retention and read/program disturb issues.

Innovation Solution

Implementing a dual-cell gray-code encoding scheme in conjunction with fractional bits-per-cell storage techniques, where unused joint data states are strategically placed to minimize bit error rates by avoiding combinations of highest and lowest data states, and using a pair of memory cells to represent non-power-of-two data states, thereby reducing unintentional shifts and errors.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If multiple bits are stored in each memory cell to increase storage density, then storage density is improved, but bit error rate increases due to difficulty in distinguishing data states

Engineering Contradiction:
Improvestorage densityVSAvoidbit error rate
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The memory cell is divided into two separate cells (first and second memory cells) that store different portions of the data. Each cell stores a subset of the total bits, reducing the number of distinguishable states required per cell while maintaining overall high storage density through joint encoding of both cells.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

An encoder is introduced as an intermediary component that performs dual-cell gray-code encoding on the data before storage. This encoder maps input data to specific joint data states across the two memory cells, ensuring that transitions between adjacent data states involve only single-bit changes, thereby reducing bit error rates.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Quantity of substance

If the number of data states is increased to represent more bits, then storage capacity is improved, but measurement precision deteriorates due to difficulty in distinguishing states

Engineering Contradiction:
Improvestorage capacityVSAvoidstate distinction accuracy
Core Design Contradiction:
Quantity of substanceVSMeasurement precision

Solution Approach 1:

The total storage capacity is segmented across two memory cells, each handling a portion of the data bits. This segmentation reduces the number of data states required in each individual cell, making state distinction easier and more accurate while preserving overall high storage capacity through combined encoding.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The encoding scheme dynamically adjusts which bits are stored in which cell based on the data being written, allowing flexible allocation of storage resources. The gray-code encoding dynamically ensures that only one bit changes between adjacent data states, optimizing state distinguishability.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS10910044B2State coding for fractional bits-per-cell memory
Publication Date: 2021.02.02 SANDISK TECHNOLOGIES LLC
  • US10910044B2 patent drawing
  • US10910044B2 patent drawing
  • US10910044B2 patent drawing

AI summary

An apparatus includes a pair of memory cells configured to represent data using joint data states where one of the joint data states comprises an error-prone joint data state. The apparatus further includes an encoder configured to convert user data into joint data states according to a dual-cell gray-code encoding scheme in which the error-prone joint data state does not encode user data.