Dual-Channel Cold Plate Assembly for Lower Chip Thermal Resistance
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Solution Overview
Problem
Existing cooling systems for microelectronic devices suffer from reduced efficiency due to high thermal resistance at interfacial boundaries and within the system components, leading to increased chip junction temperatures and reduced performance.
Innovation Solution
An integrated cooling assembly with a cold plate featuring upper and lower coolant channels, which are separated by cavity sidewalls, reduces thermal resistance by enhancing heat transfer through direct bonding or hybrid bonding techniques, using coolant fluids with additives to improve conductivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional cooling systems with thermal interface materials are used, then heat transfer is facilitated between chip and heat dissipation device, but thermal resistance at interfacial boundaries and within TIMs reduces cooling efficiency
Solution Approach 1:
The patent merges the cold plate with the packaging substrate by directly bonding them together, eliminating the need for separate thermal interface materials. The cold plate is integrated into the packaging substrate structure, creating a unified thermal management system that removes heat directly from the chip without additional thermal resistance layers.
Solution Approach 2:
The patent extracts and eliminates the thermal interface material layer from the heat transfer path. By directly bonding the cold plate to the packaging substrate, the TIM layer is removed entirely, eliminating its thermal resistance and improving overall cooling efficiency.
2Reliability
If multiple components are used between heat dissipating sources and heat dissipation devices, then heat transfer paths are established, but cumulative system thermal resistance increases and raises chip junction temperatures
Solution Approach 1:
The patent combines multiple functions into the packaging substrate: it serves as both the structural packaging component and the thermal management component. The cold plate is integrated directly into the substrate, eliminating the need for separate heat spreaders, TIMs, and mounting hardware, thus reducing component count while maintaining effective heat transfer.
3Reliability
If thermal interface materials are used to facilitate heat transfer, then thermal coupling between components is enhanced, but the combined thermal resistance of TIMs and interfacial boundary regions inhibits heat transfer
Solution Approach 1:
The patent extracts and removes the thermal interface material from the system entirely. By directly bonding the cold plate to the packaging substrate using techniques such as eutectic bonding, sintering, or soldering, the TIM layer is eliminated, removing its thermal resistance and the interfacial boundary regions that contribute to energy loss.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The integrated cooling assembly effectively reduces thermal resistance and improves heat dissipation, maintaining optimal operating temperatures for semiconductor devices, thereby enhancing energy efficiency and performance.
Implementation Method 1
The integrated cooling assembly effectively reduces thermal resistance and improves heat dissipation
Implementation Method 2
upper coolant channels and lower coolant channels form a cold plate having a two layered cooling mechanism
Data Source
AI summary
Embodiments herein provide for fluidic cooling assemblies embedded within a device package and related manufacturing methods. In one embodiment, an integrated cooling assembly includes a semiconductor device and a cold plate attached to a backside of the semiconductor device. The cold plate includes an upper portion disposed vertically adjacent to the backside of the semiconductor device and a lower portion disposed between the upper portion of the cold plate and the backside of the semiconductor device. The upper portion includes upper coolant channels defined by upper cavity sidewalls. The lower portion includes lower coolant channels defined by lower cavity sidewalls. The upper cavity sidewalls extend downwardly into regions between adjacent lower coolant channels. The lower cavity sidewalls extend upwardly into regions between adjacent upper coolant channels.