Dual-Channel DMA Controller for Seamless Mode Switching

Solution Overview

Problem

In information processing systems with network connectivity, switching between normal and standby modes often results in packet loss due to the need to stop and reset DMA controllers, leading to communication quality deterioration and increased power consumption.

Innovation Solution

A DMA controller with two channels for normal and standby modes, a mode setting register, and a channel switching part that selects the appropriate channel based on the set mode, allowing seamless switching at packet boundaries without interrupting DMA operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If the DMA controller is stopped and reset during mode switching, then the system can switch between normal and standby modes, but packet loss occurs and communication quality deteriorates

Engineering Contradiction:

Improvemode switching capabilityVSAvoidcommunication quality

Core Design Contradiction:

Adaptability or versatilityVSReliability

Solution Approach 1:

The DMA controller is divided into two separate channels: a first DMA channel for normal mode operation and a second DMA channel for standby mode operation. This segmentation allows each channel to operate independently, enabling mode switching without interrupting the DMA transfer process, thereby preventing packet loss and maintaining communication quality.

Inventive Principle:

Principle #1Segmentation

2Loss of energy

If the DMA controller is stopped during mode switching, then power consumption can be reduced in standby mode, but packet loss occurs

Engineering Contradiction:

Improvepower consumptionVSAvoidcommunication quality

Core Design Contradiction:

Loss of energyVSReliability

Solution Approach 1:

The DMA controller is divided into two separate channels: a first DMA channel for normal mode operation and a second DMA channel for standby mode operation. This segmentation allows each channel to operate independently, enabling mode switching without interrupting the DMA transfer process, thereby preventing packet loss and maintaining communication quality.

Inventive Principle:

Principle #1Segmentation

3Device complexity

If a single DMA channel is used for both normal and standby modes, then device complexity is reduced, but mode switching causes packet loss and requires stopping DMA operations

Engineering Contradiction:

ImproveDMA controller structureVSAvoidcommunication quality

Core Design Contradiction:

Device complexityVSReliability

Solution Approach 1:

The DMA controller is divided into two separate channels: a first DMA channel for normal mode operation and a second DMA channel for standby mode operation. This segmentation allows each channel to operate independently, enabling mode switching without interrupting the DMA transfer process, thereby preventing packet loss and maintaining communication quality.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The DMA controller is designed with multi-functionality to support both normal mode and standby mode operations through its two channels. The controller can selectively activate the appropriate channel based on the operational mode, providing universal functionality without requiring separate DMA controllers for each mode.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS9921983B2Direct memory access controller, control method thereof, and information processing system

Publication Date: 2018.03.20 SOCIONEXT INC

AI summary

Two channels of a main CPU channel and a sub CPU channel each including a reception channel and a transmission channel, and performing a data transfer by a DMA in accordance with a descriptor are provided, a channel switching part selects the main CPU channel or the sub CPU channel in accordance with information set at a mode setting register, and performs a switching of channels at a boundary of a packet to be transferred to thereby enable the switching of channels without interrupting a DMA operation.