Dual Channel FinFET Width Uniformity via Thermal Anneal and Oxidation
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Solution Overview
Problem
The challenge in forming dual channel CMOS FinFETs is achieving the same width and critical dimensions for silicon (Si) and silicon germanium alloy (SiGe) fins, as their different etch rates lead to varying fin widths, causing process, device, and design complexities.
Innovation Solution
A method involving forming silicon fin precursors and fin stacks with alternating silicon and silicon germanium alloy layers, followed by thermal anneal and oxidation processes to convert them into fins with uniform widths, ensuring the silicon fins and silicon germanium alloy fins have the same width and topmost surfaces are coplanar.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional etching processes are used for Si and SiGe fins, then the fins can be formed, but the different etch rates result in different fin widths and critical dimensions
Solution Approach 1:
The patent applies preliminary action by forming a mandrel structure and spacer layers before the actual fin formation. The spacer layers are deposited and patterned in advance to define the final fin width, ensuring that both Si and SiGe fins achieve uniform dimensions despite different etch rates. This pre-definition of dimensions through spacers resolves the width uniformity issue before etching occurs.
Solution Approach 2:
The patent introduces spacer layers as intermediary structures between the mandrel and the final fin. These spacers act as a mediating element that transfers the pattern from the mandrel to the fin structure, ensuring consistent width definition. The spacer material serves as a buffer that decouples the etching process from the final dimension control, allowing uniform fins to be formed despite material-specific etch rate variations.
2Productivity
If different fin widths are accepted for Si and SiGe fins, then processing can proceed, but process, device, and design complexities increase
Solution Approach 1:
The patent implements universality by using a single spacer-based patterning process that simultaneously defines the width for both Si fins and SiGe fins. The same spacer deposition and etch steps are applied universally across different device regions, creating uniform fin widths for both material types. This multi-functional approach eliminates the need for separate width-definition processes for different fin types, reducing process complexity while maintaining productivity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the formation of dual channel CMOS FinFETs with consistent fin widths, simplifying the processing and design by eliminating width variations between Si and SiGe fins, thereby enhancing device performance and reliability.
Implementation Method 1
A thermal anneal is then used to convert the fin stack into a silicon germanium alloy fin precursor
Implementation Method 2
A thermal oxidation process follows that converts the silicon fin precursor into a silicon fin and the silicon germanium alloy fin precursor into a silicon germanium alloy fin
Data Source
AI summary
A silicon fin precursor is formed in an nFET device region and a fin stack comprising alternating material portions, and from bottom to top, of silicon and a silicon germanium alloy is formed in a pFET device region. A thermal anneal is then used to convert the fin stack into a silicon germanium alloy fin precursor. A thermal oxidation process follows that converts the silicon fin precursor into a silicon fin and the silicon germanium alloy fin precursor into a silicon germanium alloy fin. Functional gate structures can be formed straddling over each of the various fins.