Dual-Channel Memory Controllers for Flash Storage I/O Throughput

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Current flash drives take an excessively long time to transfer large files due to limited write speeds, which impedes the efficient storage and transport of high-definition content.

Innovation Solution

Implementing a RAID level 0 functionality within a USB-connected storage device, utilizing dual-channel memory controllers to overlap I/O operations across multiple flash memory arrays, thereby maximizing USB bus throughput and achieving higher data transfer rates.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If traditional single-channel memory controller architecture is used, then device complexity is low, but I/O throughput is limited

Engineering Contradiction:
ImproveI/O throughputVSAvoiddevice complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The storage device is divided into multiple independent flash memory arrays (first flash memory array, second flash memory array) that can operate simultaneously. Each array is managed by dedicated memory controllers, enabling parallel I/O operations and doubling the overall throughput capacity of the device.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Multiple flash memory arrays are combined into a unified storage system with integrated memory controllers that coordinate operations across arrays. The controllers work together to manage data flow through the USB bus, achieving aggregated throughput that exceeds individual array capabilities.

Inventive Principle:
Principle #5Merging (Combining)

2Speed

If single memory controller is used, then device complexity is low, but data transfer speed is limited to 5-20 MB/sec

Engineering Contradiction:
Improvedata transfer speedVSAvoiddevice complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The single memory controller is segmented into multiple independent controllers (first memory controller, second memory controller), each capable of handling data transfers independently. This parallel architecture enables simultaneous data operations across multiple flash memory arrays, achieving aggregate transfer speeds that approach the full USB bus capability of 40 MB/sec.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system transitions from a single-dimensional sequential processing model to a multi-dimensional parallel processing model by adding multiple memory controllers operating simultaneously. This dimensional expansion in the control architecture enables proportional increases in data transfer throughput.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Loss of time

If sequential I/O operations are performed, then device complexity is low, but transfer time for large files is excessive (up to 20 minutes)

Engineering Contradiction:
Improvetransfer timeVSAvoiddevice complexity
Core Design Contradiction:
Loss of timeVSDevice complexity

Solution Approach 1:

The sequential I/O operation is segmented into parallel operations across multiple flash memory arrays. Each array processes data simultaneously through its dedicated controller, reducing the total transfer time proportionally to the number of parallel channels while maintaining manageable device complexity through modular architecture.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system maintains continuous useful action by overlapping I/O operations across multiple arrays and controllers. While one controller is transferring data, another can simultaneously perform read or write operations, ensuring that the system operates at full capacity throughout the transfer process without idle periods.

Inventive Principle:
Principle #20Continuity of useful action

Data Source

PatentUS7831758B2Accelerating input/output (IO) throughput on solid-state memory-based mass storage device
Publication Date: 2010.11.09 TAHOE RES LTD
  • US7831758B2 patent drawing
  • US7831758B2 patent drawing

AI summary

In one embodiment, a portable mass storage device may include a bus hub having a first port to couple to a bus and other ports to connect to multiple multi-channel memory controllers, where each memory controller is coupled to multiple non-volatile storage arrays, and the memory controllers can independently service the arrays to enable overlapping data transfer operations. Other embodiments are described and claimed.