Dual-Channel GAA Nanosheet Stack With Bottom Dielectric Isolation
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Solution Overview
Problem
Conventional nanosheet transistors face challenges with parasitic source/drain leakage through the substrate, which affects their electrical performance, especially at gate lengths below 12 nanometers, and require complex multi-stack integration for dual channel configurations.
Innovation Solution
The implementation of a single stack dual channel gate-all-around nanosheet structure with a strained P-type field-effect transistor (PFET) and bottom dielectric isolation N-type field-effect transistor (NFET), utilizing epitaxial silicon germanium for PFET and silicon for NFET, and employing bottom dielectric isolation to prevent leakage, while strain engineering is used for PFET and bottom dielectric isolation for NFET to suppress leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If nanosheet devices are formed on bulk substrates, then device integration is achieved, but parasitic source/drain leakage through the substrate occurs
Solution Approach 1:
The device structure is segmented into distinct regions with different substrate treatments - NFET devices have substrate access removed (segmented away) to prevent leakage, while PFET devices maintain substrate access. This segmentation allows each device type to be optimized independently, eliminating parasitic leakage paths while maintaining integration.
Solution Approach 2:
Different local qualities are applied to different device regions - the NFET region undergoes substrate removal and dielectric filling to create an isolated structure, while the PFET region maintains direct substrate contact. This local differentiation resolves the leakage issue for NFETs without affecting PFET performance.
2Adaptability or versatility
If multiple nanosheet stacks are co-integrated for PFET and NFET channels, then device functionality is achieved, but manufacturing complexity increases
Solution Approach 1:
Multiple nanosheet stacks that would traditionally be manufactured separately are merged into a single integrated stack structure. The method forms both NFET and PFET channels within one continuous nanosheet stack, using selective etching and dielectric filling to differentiate device regions. This merging dramatically simplifies manufacturing while maintaining full device functionality.
Solution Approach 2:
The single nanosheet stack structure serves multiple functions simultaneously - it provides both NFET and PFET channels, acts as a unified mechanical support structure, and enables selective device formation through post-processing. This multi-functionality reduces the number of separate manufacturing steps required.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the manufacturing process, optimizes electrical performance by eliminating parasitic leakage, and achieves effective strain engineering for PFET and bottom dielectric isolation for NFET, enhancing performance at nanoscale gate lengths.
Implementation Method 1
bottom dielectric isolation NFET
Implementation Method 2
strain engineering is used for PFET
Data Source
AI summary
Embodiments of the invention include a single stack dual channel gate-all-around nanosheet with strained PFET and bottom dielectric isolation NFET. A PFET comprising at least one silicon germanium channel is formed. An NFET comprising at least one silicon channel is formed, the PFET being positioned laterally to the NFET, the at least one silicon channel and the at least one silicon germanium channel being staggered in a vertical direction.