Dual-Channel Memory Access Control via Privilege Levels

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Solution Overview

Problem

Multi-channel memory devices face challenges in managing access privilege levels between multiple processors, leading to contention and inefficiencies in memory access operations, particularly when dealing with faster processor requests than memory systems can handle.

Innovation Solution

A dual-channel memory device architecture that employs a switch interface (SI) register to manage privilege levels, allowing interfaces to transition between access levels based on SI register bit changes, while ensuring that only higher privilege levels can access the memory array and write to status registers, thereby resolving contention and maintaining concurrent interface activity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If multiple interfaces operate concurrently to increase throughput, then memory access efficiency is improved, but contention between interfaces occurs leading to access conflicts

Engineering Contradiction:
Improvememory access throughputVSAvoidaccess conflict prevention
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent introduces a privilege level management mechanism as an intermediary between multiple interfaces and the memory array. Each interface is assigned a privilege level (first privilege level for write access, second privilege level for read-only access), and the system mediates access requests by comparing privilege levels against required access permissions. This mediator prevents contention by blocking incompatible access requests before they reach the memory array, allowing concurrent operation without conflicts.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If privilege levels are implemented to control interface access, then access contention is resolved, but interface operation complexity increases

Engineering Contradiction:
Improveaccess privilege managementVSAvoidinterface control mechanism
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent implements privilege level management by changing the parameter of interface permissions into discrete privilege levels. Each interface is assigned a specific privilege level (first or second), and access control is achieved by comparing these parameter values against access requirements. This parameter-based approach simplifies the control mechanism compared to complex arbitration logic, as the privilege level assignment and comparison provide a straightforward method for resolving access contention without requiring sophisticated control circuits.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS9405475B2Multi-interface memory with access control
Publication Date: 2016.08.02 MICRON TECHNOLOGY INC
  • US9405475B2 patent drawing
  • US9405475B2 patent drawing
  • US9405475B2 patent drawing

AI summary

Subject matter disclosed herein relates to a memory device, and more particularly to a multi-channel memory device and methods of selecting one or more channels of same.