Dual Channel Memory Package with Co-Support and Stacked Interconnects
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current microelectronic packaging technologies face challenges in efficiently interconnecting multiple chips within a compact space, particularly in portable devices and data servers, where the need for high bandwidth and reduced power consumption is critical, while maintaining a small assembly size.
Innovation Solution
A microelectronic package design featuring a support element with oppositely-facing surfaces and substrate contacts, where microelectronic elements are stacked and electrically coupled, with terminals arranged to carry address and data information, allowing for independent operation of memory channels and optimized interconnect lengths to enhance signal speed and reduce signal propagation time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple chips are assembled in a multi-chip memory package, then bandwidth and functionality are improved, but package size and interconnection complexity increase
Solution Approach 1:
The patent transitions from planar chip arrangements to a three-dimensional stacked configuration, placing memory chips vertically above one another. This vertical stacking enables multiple chips to occupy a smaller footprint area while maintaining high bandwidth through multiple simultaneous access channels, effectively resolving the contradiction between increased functionality and package size.
Solution Approach 2:
The patent implements a nested structure where memory chips are stacked vertically, with each chip positioned above the previous one like nested dolls. This nesting approach allows multiple independent memory modules to be integrated within a compact volume, achieving high bandwidth without proportionally increasing package area.
2Productivity
If multiple chips are interconnected with numerous I/O connections, then functionality and bandwidth are improved, but interconnection structure complexity and size increase
Solution Approach 1:
The patent divides the interconnection structure into separate, independent channels, with each channel serving specific memory chips. This segmentation allows for simplified individual channel designs while achieving high overall bandwidth through parallel operation of multiple channels, reducing the complexity of any single interconnection path.
Solution Approach 2:
The patent designs the interconnection structure to serve multiple functions: the same basic channel architecture supports both address signals and data signals, and can accommodate different memory chip configurations. This multi-functionality reduces overall structural complexity by avoiding the need for specialized interconnection paths for each function.
3Area of moving object
If chip size is reduced to fit more chips in compact devices, then portability is improved, but signal transmission quality and electrical connection reliability deteriorate
Solution Approach 1:
By stacking chips vertically rather than arranging them horizontally, the patent reduces the planar footprint while maintaining adequate signal transmission distances through the vertical dimension. The shortened horizontal trace lengths in the stacked configuration reduce signal degradation despite smaller overall package size.
Solution Approach 2:
The patent introduces intermediate connection structures, such as redistribution layers and intermediary substrate contacts, that facilitate reliable electrical connections between stacked chips. These intermediaries compensate for the challenges of miniaturization by providing robust signal paths despite reduced chip dimensions.
Data Source
AI summary
A microelectronic package can include a support element having first and second surfaces and substrate contacts at the first or second surface, zeroth and first stacked microelectronic elements electrically coupled with the substrate contacts, and terminals at the second surface electrically coupled with the microelectronic elements. The second surface can have a southwest region encompassing entire lengths of south and west edges of the second surface and extending in orthogonal directions from the south and west edges one-third of each distance toward north and east edges of the second surface, respectively. The terminals can include first terminals at a southwest region of the second surface, the first terminals configured to carry address information usable by circuitry within the microelectronic package to determine an addressable memory location from among all the available addressable memory locations of the memory storage arrays of at least one of the zeroth or first microelectronic elements.