Dual Channel Memory Architecture with Shared Address Bus
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Solution Overview
Problem
Existing dual-channel memory architectures face design challenges due to increased complexity and pin count, which leads to higher costs and incompatibility with existing systems, when upgrading from single wide-channel to dual narrow-channel interfaces.
Innovation Solution
A dual channel memory architecture with a shared address/control bus and alternating clock signals of opposite polarity between memory devices, allowing for efficient data transfer over separate narrow data buses without the need for additional interface pins, thereby reducing circuit complexity and maintaining backward compatibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If dual channel memory architecture is implemented with separate address/control buses, then data transfer efficiency is improved, but interface pin count and circuit complexity increase
Solution Approach 1:
The patent combines the address and control signal lines into a shared bus that is time-multiplexed between two memory channels. Instead of providing separate address and control buses for each channel, a single shared bus carries address signals for one channel during one clock cycle and control signals for the other channel during the next clock cycle, thereby reducing pin count while maintaining dual channel functionality
Solution Approach 2:
The patent implements periodic time-multiplexing where the shared address/control bus alternates between serving different channels in a regular pattern. The bus is assigned to Channel 0 during even clock cycles and to Channel 1 during odd clock cycles, creating a periodic allocation pattern that allows efficient resource sharing while maintaining independent access to both channels
2Productivity
If dual channel memory architecture is implemented, then burst access performance is improved, but interface pin requirements increase
Solution Approach 1:
The patent merges the address and control signal lines into a shared bus that is time-multiplexed between two memory channels. Instead of providing separate address and control buses for each channel, a single shared bus carries address signals for one channel during one clock cycle and control signals for the other channel during the next clock cycle, thereby reducing pin count while maintaining dual channel functionality
Solution Approach 2:
The shared address/control bus serves multiple functions and multiple channels. The same physical bus infrastructure is used to address memory locations in Channel 0 and to control operations in Channel 1, making the bus a universal resource that performs multiple roles rather than having dedicated separate buses for each function and channel
3Productivity
If conventional dual channel interface is used, then data transfer capability is improved, but backwards compatibility is lost
Solution Approach 1:
The shared address/control bus serves multiple functions and multiple channels. The same physical bus infrastructure is used to address memory locations in Channel 0 and to control operations in Channel 1, making the bus a universal resource that performs multiple roles rather than having dedicated separate buses for each function and channel
Data Source
AI summary
Apparatuses and methods for dual channel memory architecture with reduced interface pin requirements are presented. One memory architecture includes a memory controller, a first memory device coupled to the memory controller by a shared address bus and a first clock signal, and a second memory device coupled to the memory controller by the shared address bus and a second clock signal, where the polarity of the second clock signal is opposite of the first clock signal. A method for performing data transactions is presented. The method includes providing addressing signals over a shared address bus to a first memory device and a second memory device, providing clock signals to the memory devices which are reversed in polarity, where the clock signals are derived from a common clock signal, and transferring data to the memory devices over separate narrow data buses in an alternating manner based upon the clock signals.